Register Space - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

Document ID
PG230
Release Date
2023-11-03
Version
2.2 English

The PHY configuration data is implemented as a set of distributed registers that can be read or written from the AXI4-Lite interface. These registers are synchronous to the AXI4-Lite domain.

Any bits not specified in the following register tables are considered reserved and return zero upon read. The power-on reset values of control registers are zero unless specified in the definition. Only address offsets are listed in the following tables, and the base address is configured by the AXI interconnect at the system level.

For more information, see the following documents:
  • 7 Series FPGAs GTX/GTH Transceivers User Guide (UG476)
  • UltraScale Architecture GTH Transceivers User Guide (UG576)
  • 7 Series FPGAs GTP Transceivers User Guide (UG482)
  • UltraScale Architecture GTY Transceivers User Guide (UG578)
Table 1. Register Address Space
Address (hex) Register
0x0000 Version Register (VR)
0x0004 Reserved
0x0008 Reserved
0x000C Bank Select (BSR)
Shared Features and Resets
0x0010 Reference Clock Selection (RCS)
0x0014 PLL Reset (PR)
0x0018 PLL Lock Status (PLS)
0x001C TX Initialization (TXI)
0x0020 TX Initialization Status (TXIS)
0x0024 RX Initialization (RXI)
0x0028 RX Initialization Status (RXIS)
0x002C IBUFDS GTxx Control (IBUFDSGTxxCTRL)
Power Down
0x0030 Power Down Control (PDC)
0x0034 Reserved
Loopback
0x0038 Loopback Control (LBC)
0x003C Reserved
Dynamic Reconfiguration Port (DRP)
0x0040 DRP CONTROL Channel1 (DRPCCH1)
0x0044 DRP CONTROL Channel2 (DRPCCH2)
0x0048 DRP CONTROL Channel3 (DRPCCH3)
0x004C DRP CONTROL Channel4 (DRPCCH4)
0x0050 DRP STATUS Channel1 (DRPSCH1)
0x0054 DRP STATUS Channel2 (DRPSCH2)
0x0058 DRP STATUS Channel3 (DRPSCH3)
0x005C DRP STATUS Channel4 (DRPSCH4)
0x0060 DRP CONTROL Common (DRPCC)
0x0064 DRP STATUS Common (DRPSC)
0x0068 - 0x006C Reserved
Transmitter Functions
0x0070 TX Control (TXC)
0x0074 1 TX Buffer Bypass Control (TXBBC)
0x0078 TX Status (TXS)
0x007C TX DRIVER Control – Channel 1 and 2 (TXDC12)
0x0080 TX DRIVER Control – Channel 3 and 4 (TXDC34)
0x0084 RX Symbol Error Counter – Channel 1 and 2
0x0088 RX Symbol Error Counter – Channel 3 and 4
0x008C to 0x009C Reserved
Receiver Functions
0x0100 RX Control (RXC)
0x0104 RX Status (RXS)
0x0108 RX Equalization and CDR
0x010C 2 RX TDLOCK VALUE
Interrupts Registers
0x0110 Interrupt Enable Register (IER)
0x0114 Interrupt Disable Register (IDR)
0x0118 Interrupt Mask Register (IMR)
0x011C Interrupt Status Register (ISR)
TXUSRCLK Clocking
0x0120 MMCM TXUSRCLK Control/Status (MMCM_TXUSRCLK_CTRL)
0x0124 DRP CONTROL MMCM TXUSRCLK
0x0128 DRP STATUS MMCM TXUSRCLK
0x0134 BUFGGT TXUSRCLK Control (BUFGGT_TXUSRCLK_CTRL)
0x0138 MISC TXUSRCLK Control (MISC_TXUSRCLK_CTRL)
0x0140 MMCM RXUSRCLK Control/Status (MMCM_RXUSRCLK_CTRL)
0x0144 DRP CONTROL MMCM RXUSRCLK
0x0148 DRP STATUS MMCM RXUSRCLK
0x0154 BUFGGT RXUSRCLK Control (BUFGGT_RXUSRCLK_CTRL)
0x0158 MISC RXUSRCLK Control (MISC_RXUSRCLK_CTRL)
Clock Detector (HDMI)
0x0200 Control Register
0x204 Status Register
0x0208 Frequency Counter Timeout
0x020C Transmitter Frequency
0x0210 Receiver Frequency
0x0214 Transmitter Timer
0x0218 Receiver Timer
0x021C DRU Frequency
Data Recovery Unit
0x0300 Control Register
0x0304 Status Register
0x0308 Center Frequency Low Register – All Channels
0x030C Center Frequency High Register – All Channels
0x0310 Gain Register – All Channels
TX TMDS Pattern Generator
0x0340 Control Register
  1. For the DisplayPort protocol, the GT Wizards internal FSM handles these status bits. This register field is unused.
  2. For the DisplayPort protocol, this register field is unused.