For GTHE3, GHE4, and GTYE4, the PHY generates an XDC
file to place the GT channels and output data pins (optional fourth GT as TMDS). The PHY
also constrains the clocks out of the GT. The required constraints include the clock and
location. The following clock ports are not constrained by the PHY, but are dependent on
the application-specific requirements:
- RX reference clock in
- TX reference clock in
- TX TMDS clock (when the fourth GT is not used in TMDS)
- RX TMDS clock out
For GTX2, the GT and output clock constraints are not created by the PHY and must be constrained by the system XDC file. See sample designs for examples of constraining the HDMI solution.