CPLL Use - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)
Document ID
PG230
Release Date
2023-11-03
Version
2.2 English

Because the largest multiplier that can be applied by the CPLL is 40, the minimum TMDS clock frequency that the CPLL can support is 50 MHz. Video formats that have a TMDS clock frequency of less than 50 MHz are not supported by the CPLL.

Note: The largest multiplier (40) is achieved by CPLL CPLL_FBDIV_45 (N1)=5 and CPLL_FBDIV (N2)=8. Note that CPLL_FBDIV=8 is only approved by AMD to be used in the Video PHY Controller IP for HDMI and DisplayPort protocols.

When the GT driver detects that the TMDS clock frequency is less than 50 MHz, it enables the NI-DRU to receive these low bit rates that are less than 500 Mbps. The NI-DRU runs at 2.5 Gbps, which enables it to recover line rates that the CPLL cannot support.

For TMDS clock frequencies greater than 50 MHz, a multiplier of 10X, 20X, or 40X is applied to keep the VCO frequency in the proper range as shown in the following table.

Table 1. UltraScale GTH CPLL Use
TMDS Clock Frequency (MHz) CPLL Refclk Divider CPLL Multiplier VCO Frequency Notes
<50

TX: Line Rate Dependent

RX: 2

TX: Line Rate Dependent

RX: 16

TX: Line Rate Dependent

RX: 2.5 GHz

TX: Oversampling

RX: NI-DRU is used
50 to 156.25 1 40

2.0 to 6.25 GHz

 CDR is used
100 to 312.5 1 20

2.0 to 6.25 GHz

 CDR is used
312.5 to 340 1 10 3.125 to 3.4 GHz CDR is used
Important: Using the CPLL, the HDMI RX can receive the most valid video format up to a maximum line rate of 6 Gbps using the NI-DRU or the native CDR.

The following table is for illustration only. For unlisted color formats, support might be possible if the VCO frequency range does not restrict them.

Table 2. CPLL Support of RGB and YCbCr 4:4:4 Video Formats
Resolution (Hz) Bits Per Pixel
24 30 36 48
480i60 DRU DRU DRU √
576i50 DRU DRU DRU √
1080i50 √ √ √ √
1080i60 √ √ √ √
480p60 DRU DRU DRU √
576p50 DRU DRU DRU √
720p50 √ √ √ √
720p60 √ √ √ √
1080p24 √ √ √ √
1080p25 √ √ √ √
1080p30 √ √ √ √
1080p50 √ √ √ √
1080p60 √ √ √ √
2160p24 √ √ √ √
2160p25 √ √ √ √
2160p30 √ √ √ √
2160p60 √ (1) (1) (1)
VGA 60 DRU DRU DRU 3 √ 3
SVGA 60 DRU DRU √ √
XGA 60 √ √ √ √
SXGA 60 √ √ √ √
WXGA 60 √ √ √ √
WXGA + 60 √ √ √ √
UXGA 60 √ √ √ √
WUXGA 60 √ √ √ √
WSXGA 60 √ √ √ √
  1. This format is not supported because it exceeds the maximum line rate of HDMI 2.0.
  2. This format is supported for transmit but is not currently supported by the receiver.
  3. TX does not support VGA 12 and 16 BPC at 4 PPC due to DCM limitations.

When using the two Quad PLL (QPLL) types for the HDMI transmitter and receiver, line rate restrictions are introduced due to the VCO range and limited set of multipliers of the QPLL. The Video PHY Controller core driver dynamically switches between QPLL0 and QPLL1 to overcome these restrictions with QPLL0 having the priority if the TMDS clock frequency falls within the valid range of QPLL0 and QPLL1. For the transmitter, the Video PHY Controller core driver uses oversampling and the dynamic QPLL switching to work around the QPLL limitations.