7 Series GTPE2 HDMI Implementation - 2.2 English

Video PHY Controller LogiCORE IP Product Guide (PG230)

Document ID
PG230
Release Date
2023-11-03
Version
2.2 English

The GTP transceiver in 7 series FPGAs has two types of PLLs, the PLL0 and PLL1 of similar characteristics. All four transceivers in the Quad share both PLL types. There is no dedicated PLL for each transceiver channel for GTPE2. The Video PHY IP enables you to choose whether the PLL0 or the PLL1 is used by the transmitter. The receiver should use the other PLL that TX does not use.

The PLL0/1 voltage controlled oscillator (VCO) must run in the range of 1.6 GHz to 3.3 GHz. The VCO frequency is dependent upon the TMDS clock frequency. The PLL0/1 can apply a limited set of multipliers to the TMDS clock frequency. The GT driver measures the TMDS clock frequency and attempts to find a valid multiplier that results in a VCO frequency that is within the allowed range.

Because the largest multiplier that the PLL0/1 applies is 20, the minimum TMDS clock frequency that the PLL0/1 can support is 80 MHz. Video formats that have a TMDS clock frequency of less than 80 MHz are not supported by the PLL0/1. When the GT driver detects that the TMDS clock frequency is less than 80 MHz, it enables the NI-DRU to receive these low bit rates that are less than 0.8 Gbps. The NI-DRU runs at 2.5 Gbps, which enables it to recover line rates that the PLL0/1 cannot support. For TMDS clock frequencies greater than 80 MHz, a multiplier of 10X or 20X is applied to keep the VCO frequency in the proper range as shown in the following table.

Table 1. 7 Series GTP PLL0/1 Usage
TMDS Clock Frequency (MHz) PLL0/1 Refclk Divider PLL0/1 Multiplier VCO Frequency Notes
<80

TX: Line Rate Dependent

RX: 2

TX: Line Rate Dependent

RX: 25

TX: Line Rate Dependent

RX: 2.5 GHz

TX: Oversampling

RX: NI-DRU is used

80 to 165 1 20 1.6 to 3.3 GHz CDR is used
165 to 330 1 10 1.65 to 3.3 GHz CDR is used
Important: Using the PLL0/1, the HDMI RX can receive the most valid video format, using the NI-DRU or the native CDR, up to a maximum line rate of 6 Gbps. HDMI Video PHY Controller does not support parts with -1, -1L, and -2LE (0.9V) speed grades because the maximum line rate for those devices is only 3.75 Gbps.

The PLL0/1 can support all video formats. It has no "holes." However, the PLL0/1 does require the use of the NI-DRU to cover any format that has a TMDS clock below 80 MHz. The following table shows the standard formats that the PLL0/1 supports, indicating which requires the DRU.

The following table is for illustration only. For unlisted color formats, support might be possible if the VCO frequency range does not restrict them.

Table 2. PLL0/1 Support of RGB and YCbCr 4:4:4 Video Formats
Resolution (Hz) Bits Per Pixel
24 30 36 48
480i60 DRU DRU DRU DRU
576i50 DRU DRU DRU DRU
1080i50 DRU
1080i60 DRU
480p60 DRU DRU DRU DRU
576p50 DRU DRU DRU DRU
720p50 DRU
720p60 DRU
1080p24
1080p25
1080p30
1080p50
1080p60
2160p24
2160p25
2160p30
2160p60 - (1) (1) (1)
vgap60 DRU DRU DRU 3 DRU 3
svgap60 DRU DRU DRU
xgap60 DRU
sxgap60
wxgap60 DRU
wxga+p60
uxgap60 (2)
wuxgap60
wsxga+p60
  1. This format is not supported because it exceeds the maximum line rate of HDMI 2.0.
  2. This format is supported for transmit but is not currently supported by the receiver.
  3. TX does not support VGA 12 and 16 BPC at 4 PPC due to Digital Clock Manager limitations.