Simulating an AI Engine Graph Application - 2021.2 English

This chapter describes the various execution targets available to simulate AI Engine applications at different levels of abstraction, accuracy, and speed. AI Engine graphs can be simulated in four different simulation environments.

The x86 simulator is a fast-functional simulator as described in x86 Functional Simulator. It should be used to functionally simulate your AI Engine graph and is useful for functional development and verification of kernels and graphs. It, however, does not provide timing, resource, or performance information.

The AI Engine simulator (aiesimulator) models the timing and resources of the AI Engine array, while using transaction-level SystemC models for the NoC, DDR memory. This allows for faster performance analysis of your AI Engine applications and accurate estimation of the AI Engine resource use, with cycle-approximate timing information.

In both x86 functional simulator and AI Engine simulator, PL interface to AI Engine can be exercised through untimed external traffic. Similarly, both use the user graph’s main() function as C-test bench to configure and control the AI Engine. This test bench data input and output is not timed, and the user graph’s main() function acts as a virtual simulation platform.

When you want a fast functional simulation of the entire system including the AI Engine graph, the PL logic along with XRT-based host application to control the AI Engine and PL, you should use the Vitis™ software emulation flow. The software emulation flow enables using HLS-based kernels or C-models of RTL based kernels to be interfaced with AI Engine graph and controlled using host code which can also be run on hardware. This flow includes the x86 functional model of the AI Engine, and Arm® QEMU emulator modeling the PS (untimed).

Finally, when you are ready to simulate the entire system including AI Engine graph and PL logic along with XRT-based host application to control the AI Engine and PL, for a specific board and platform, you should use the Vitis hardware emulation flow. This flow includes the SystemC model of the AI Engine, transaction-level SystemC models for the NoC, DDR memory, PL Kernels (RTL), and PS (running on QEMU). You can also include RTL logic and test bench PL logic for your platform or design.

The following table lists the four simulation flows and whether they support functional or performance level debug, and the level of support for source code debug. It also recommends the usage of these simulation flows in appropriate stages of your AI Engine design development.