The NIDRU is designed with efficient structures only (adders, multipliers, accumulators, and shifters). The resource requirements for UltraScale+ FPGAs are summarized in Table: Hardware Resources Required for the NIDRU in UltraScale+ FPGAs.
|
Synthesis Type |
Eye Scan |
Flip-Flops |
LUTs |
BUFGs(1) |
|---|---|---|---|---|
|
4 |
0 |
251 |
300 |
1 |
|
1 |
556 |
585 |
||
|
2 |
697 |
689 |
||
|
20 |
0 |
308 |
356 |
1 |
|
1 |
631 |
715 |
||
|
2 |
781 |
860 |
||
|
32 |
0 |
973 |
1,178 |
1 |
|
1 |
1,846 |
2,363 |
||
|
2 |
2,271 |
2,906 |
||
|
64 |
0 |
1,908 |
2,526 |
1 |
|
1 |
3,802 |
5,449 |
||
|
2 |
4,743 |
6,863 |
||
|
128 |
0 |
3,484 |
5,187 |
1 |
|
1 |
7,185 |
11,257 |
||
|
2 |
9,031 |
14,223 |
||
|
Notes: 1.Only one BUFG is required even if many channels are being set up, and even if all are working at different data rates. 2.These results were obtained using Vivado Design Suite, version 2016.4. The strategy used for the synthesis and implementation was Default and the CLK period was 6.4 ns. |
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