NIDRU Block Diagram and Pinout

Clock and Data Recovery Unit based on Deserialized Oversampled Data (XAPP1240)

Document ID
XAPP1240
Release Date
2022-11-04
Revision
3.1 English

This section describes the structure of the NIDRU wrapper and its pinout. The wrapper structure is shown in This Figure. Only relevant ports are shown.

Figure 1:      NIDRU Wrapper Block Diagram

X-Ref Target - Figure 1

X24544-Page-1.jpg

The DIN port receives raw oversampled data from a SelectIO™ interface or a SerDes set in lock-to-reference mode. The width of the oversampled data is programmable by the DT_IN_WIDTH attribute. The value of the DT_IN_WIDTH attribute can be set to 4, 20, or 32 bits. The NIDRU bit-ordering convention is the same as the SerDes, where the LSB is the oldest bit(1). The phase detector (PD) looks for transitions in the incoming data, continuously comparing the phase of the incoming data with the phase of the internal numerically-controlled oscillator (NCO). The digital error signal generated by the PD and filtered out by the low-pass filter (LP) corrects the NCO frequency to minimize the phase error, thus realizing the phase-locked loop (PLL) functionality of the NIDRU [Ref 1] [Ref 2]. Based on the NCO output, the sample selector block (SS) selects the samples that are more closely positioned to the middle of the eye. There can be up to 10 valid samples in each REFCLK cycle, which are placed by the SS on the SAM output. SAMV indicates the number of valid samples on SAM at each clock cycle. To simplify the connection between the NIDRU and the user application, a barrel shifter is provided in the wrapper, where the output data width can be programmed using the WDT_OUT attribute. All blocks in the NIDRU wrapper are synchronized to REFCLK.

The NIDRU operates in parallel over the incoming data, generally producing more than one bit output for each clock cycle. The relationship between the operating frequency (REFCLK) and the incoming data rate dictates the maximum number of bits processed per clock cycle, NMAX, according to This Equation:

Equation 1      xapp1240-k7-us-clk-data-recovery00002.jpg

Three example user configurations of fREFCLK and oversampling rate are considered here and yield these results for NMAX:

Fast Ethernet with fREFCLK = 125 MHz, oversampling at 2.5 Gb/s: NMAX = 2.

STM1 with fREFCLK = 125 MHz, oversampling at 2.5 Gb/s: NMAX = 2.

Fast Ethernet with fREFCLK = 155.52 MHz, oversampling at 3.1 Gb/s: NMAX = 1.

If N > 1, the barrel shifter eases the interfacing of the DRU to a fixed-width FIFO. If N = 1 and the user application has 1-bit width only, the barrel shifter is not needed.

Table: NIDRU Configuration Attributes describes the NIDRU configuration attributes. NIDRU ports are described in Table: NIDRU Ports.

Table  1:       NIDRU Configuration Attributes

Attribute Name

Type/Range

Description

Comment

Configuration Section

WDT_OUT

Integer
from 2 to 64

Output data width

Output width for the bus DOUT.

DT_IN_WIDTH

Integer
4, 20, 32, 64, or 128

Input data width

Output width for the bus DT_IN.

EN_CENTER_F_ATTR

Standard logic

Enables use of Center_f_attr

When set to 1, CENTER_F_ATTR is used as CENTER_F. When set to 0, the CENTER_F port is used.

CENTER_F_ATTR

Standard logic
vector
36 down to 0

Attribute configuration for CENTER_F

CENTER_F_ATTR can be used instead of CENTER_F depending on the value of
EN_ CENTER_F_ATTR.

EN_G1_ATTR

Standard logic

Enables use of G1_ATTR

When set to 1, CENTER_F_ATTR is used as CENTER_F. When set to 0, the CENTER_F port is used.

G1_ATTR

Standard logic
vector
4 down to 0

Attribute configuration for G1

G1_ATTR can be used instead of G1 depending on the value of EN_ G1_ATTR.

EN_G2_ATTR

Standard logic

Enables use of G2_ATTR

When set to 1, CENTER_F_ATTR is used as CENTER_F. When set to 0, the CENTER_F port is used.

G2_ATTR

Standard logic
vector
4 down to 0

Attribute configuration for G2

G2_ATTR can be used instead of G2 depending on the value of EN_G2_ATTR.

EN_G1_P_ATTR

Standard logic

Enables use of G1_P_ATTR

When set to 1, CENTER_F_ATTR is used as CENTER_F. When set to 0, the CENTER_F port is used.

G1_P_ATTR

Standard logic
vector
4 down to 0

Attribute configuration for G1_P

G1_P_ATTR can be used instead of G1_P depending on the value of EN_G1_P_ATTR.

EN_SHIFT_S_PH_ATTR

Standard logic

Enables use of SHIFT_S_PH_ATTR

When set to 1, CENTER_F_ATTR is used as CENTER_F. When set to 0, the CENTER_F port is used.

SHIFT_S_PH_ATTR

Standard logic
vector
7 down to 0

Attribute configuration for SHIFT_S_PH

SHIFT_S_PH_ATTR can be used instead of SHIFT_S_PH depending on the value of EN_SHIFT_S_PH_ATTR.

EN_EN_INTEG_ATTR

Standard logic

Enable port EN_INTEG

When set to 1 enables EN_INTEG port. When set to 0, the EN_INTEG port is connected to EN_INTEG_ATTR.

EN_INTEG_ATTR

Standard logic

Attribute configuration for EN_INTEG

See EN_EN_INTEG_ATTR.

EN_EN

Standard logic

Enables the EN port

The EN port can be disabled by setting EN_EN=1, reducing the complexity of the circuit.

ENABLE_LTR_PORT

Standard logic

Enables lock to reference mode

When set to 1, the port LTR can be used to disable the tracking mechanism (LTR = 1).

Eye Scan Section

PH_NUM

Integer
from 0 to 2

Number of extra sampling
phases

0: No eye scan logic is instantiated.
1: Eye scan logic with one extra phase.
2: Eye scan logic with two extra phases.

Logic Optimization Section

S_MAX

Integer
from 1 to 64

Expected maximum number of
extracted samples per clock cycle

See NIDRU Usage Model for configuration instructions for this port.

Set S_MAX ³ NMAX.
Setting S_MAX to 2 if DT_IN_WIDTH = 4
or to 10 if DT_IN_WIDTH = 20
or to 16 if DT_IN_WIDTH = 32 works for all cases.

S_MAX_EYE

Integer
from 1 to 64

Maximum number of samples extracted by the Eyescan controller

See NIDRU Usage Model for configuration instructions for this port.

MASK_CG

Standard logic
vector
15 down to 0

Mathematical precision of the
generated coefficients

See NIDRU Usage Model for configuration instructions for this port.

Setting MASK_CG to all ones forces NIDRU to use maximum precision.

MASK_PD

Standard logic
vector
15 down to 0

Mathematical precision of the
PD calculations

See NIDRU Usage Model for configuration instructions for this port.

Setting MASK_PD to all ones forces NIDRU to use maximum precision.

MASK_VCO

Standard logic
vector
36 down to 0

Mathematical precision of the
NCO output

See NIDRU Usage Model for configuration
instructions for this port.

Setting MASK_VCO to all ones forces NIDRU to use maximum precision.

Table: NIDRU Ports describes the NIDRU ports. NIDRU configuration attributes are described in Table: NIDRU Configuration Attributes.

Table  2:       NIDRU Ports

Pin Name

Type

Description

Comment

Data Ports

DT_IN

Input
4, 20, 32, 64, or 128 bits wide

Input data from SerDes or SelectIO interface

Bit 0 is the oldest.

EN

Input

Enable

Enables all processes of the NIDRU.

CLK

Input

Clock

Clock for all NIDRU processes.

RST_FREQ

Input

Integral path reset

Resets the integral path in the NIDRU.

RECCLK

Output
DT_IN_WIDTH bits

Recovered clock

This is the recovered clock to be serialized by a TX SerDes or a SelectIO interface. In terms of serialization order, bit 0 has to be serialized first.

EN_OUT

Output

Output data valid

When data on DOUT is valid, the NIDRU sets EN_OUT to 1.

DOUT

Output
WDT_OUT bits

Output data

Output data for the user application. The width of DOUT is programmable through the attribute WDT_OUT.

Config Ports

CENTER_F

Input
37 bits

Center frequency at which the NIDRU operates

See NIDRU Usage Model for configuration instructions for this port.

G1

Input
5 bits

Direct gain

See NIDRU Usage Model for configuration instructions for this port.

G1_P

Input
5 bits

Integral pre-gain

See NIDRU Usage Model for configuration instructions for this port.

G2

Input
5 bits

Integral post-gain

See NIDRU Usage Model for configuration instructions for this port.

LTR

Input

Lock to reference mode

See attribute EN_LTR_PORT.

Eye Scan Ports

AUTOM

Input

Auto/manual mode

Setting to 1 enables the embedded eye scan controller. Setting to 0 allows performing eye scan manually.

START_EYESCAN

Input

Start eye scan

Pulse for at least 1 clock cycle to request an eye scan. Any eye scan request while EYESCAN_BUSY = 1 is discarded.

EYESCAN_BUSY

Output

Eye scan is operating

When set to 1, eye scan is being acquired.

TRIGGER_MODE

Input

Eye acquisition mode

See One-Dimensional Eye Scan.

EYE_AP

Output

The eye aperture can be read here.

This value is updated each time the signal EYSCAN_BUSY goes down.

RST_PH_0

Input

Phase 0 reset

See One-Dimensional Eye Scan.

RST_PH_1

Input

Phase 1 reset

RST_PH_SAMP

Input

Sampling phase reset

ERR_PH_0

Output
7 bits

Error number from phase 0

ERR_PH_1

Output
7 bits

Error number from phase 1

PH_0

Input
8 bits

Phase 0 position

PH_1

Input
8 bits

Phase 1 position

PH_0_SCAN

Output
8 bits

Current phase 0 being scanned

PH_1_SCAN

Output
8 bits

Current phase 1 being scanned

WAITING_TIME

Input
48 bits

Waiting time for each sample

ERR_COUNT_PH_0

Output
52 bits

Errors accumulated in PH_0

EN_ERR_COUNT_PH_0

Output

Valid signal for ERR_COUNT_PH_0

ERR_COUNT_PH_1

Output
52 bits

Errors accumulated in PH_1

EN_ERR_COUNT_PH_1

Output

Valid signal for ERR_COUNT_PH_1

Debug Ports

PH_OUT

Output

NCO phase output

Debug outputs.

INTEG(31:0)

Output

Integral-branch output

DIRECT(31:0)

Output

Direct-branch output

CTRL(31:0)

Output

NCO control signal

AL_PPM

Output

PPM alarm

When set to 1, the input frequency has exceeded the range for which NIDRU has been configured. This signal is not latched.

RST

Input

Reset

Resets NIDRU, except for the integral path.

PH_EST_DIS

Input

Phase error estimation method

Debug input. Set to 0.

EN_INTEG

Input

Enable for the integral path

Debug input. Set to 1.

VER

Output
8 bits

Version

NIDRU version. The version delivered with this application note is 9.

SAMV

Output
7 bits

Number of samples out

At each clock cycle, the NIDRU reports how many bits have been extracted. SAMV is connected to the barrel shifter in the wrapper.

SAM

Output
10 or 16 bits

Samples out

At each clock cycle, NIDRU reports the SAMV bits which have been extracted. They are placed in the lowest portion of SAM. SAM is connected in the wrapper to the barrel shifter.

CF_ADD

Input, debug

Set to 0.

Reserved.

SHIFT_S_PH

Input
8 bits

Sampling phase shift

Reserved. Adjusts the position of the sampling phase inside the eye. Resolution is 256 steps. Default is 0.