When clock phase logic is enabled, extracted audio samples along with the correspoding clock phase information are stored in the internal buffers. Audio samples are output on AXI4-Stream interfacewhen the clock phase matches with the current line and sample position. This ensures that Audio samples are evenly distributed (as per sample rate) on the AXI4-Stream interface.
When clock phase logic is disabled, audio samples are output on AXI4-Stream interface as and when they are extracted.
Note: Some equipment may not produce the correct clock phase in which case UHD-SDI Audio
(Extract) cannot match the decoded clock phase with the line and sample number. UHD-SDI
Audio (Extract) has the logic to handle this case by flushing the samples whose clock
phase cannot be matched.