Core Specifics |
Supported Device Family
1
|
Versal®
ACAP,
UltraScale+™
Families,
Zynq®
UltraScale+™ MPSoC, Kintex UltraScale,
Virtex®
UltraScale™
,
7 series,
2
Zynq®-7000 SoC
|
Supported User Interfaces |
AXI4-Stream, AXI4-Lite, and Native SDI |
Resources |
Performance and Resource Use web page
|
Provided with
Core
|
Design Files |
Register Transfer Lever (RTL) |
Example Design |
Verilog |
Test Bench |
Not Provided |
Constraints File |
XDC |
Simulation Model |
Not Provided |
Supported S/W Driver
2
|
Standalone and Linux |
Tested Design
Flows
3
|
Design Entry |
Vivado Design Suite
|
Simulation |
For supported simulators, see the
Xilinx®
Design
Tools: Release Notes Guide. |
Synthesis |
Vivado Synthesis |
Support |
Release Notes and Known Issues |
Master Answer Record: 70290. |
All Vivado IP Change
Logs |
Master Vivado IP Change Logs:
72775
|
Xilinx
Support web page
|
- For a complete list of supported devices, see
the
Vivado®
IP catalog.
-
Artix®-7 device is not
supported.
- Standalone driver details can be found in the
Vitis™
directory
(<install_directory>/vitis/<release>/data/embeddedsw/doc/xilinx_drivers.htm).
Linux OS and driver support information is available from the Xilinx Wiki
page.
- For the supported versions of the tools, see
the Xilinx Design Tools: Release Notes
Guide.
|