Status and Control Ports - 1.0 English

Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321)
Document ID
PG321
Release Date
2022-10-26
Version
1.0 English
Table 1. Clocking Wizard Status and Control Ports
Port Name I/O Description
reset/resetn Input Reset (active- High)/Resetn (active-Low): When asserted, asynchronously clears the internal state of the primitive, and causes the primitive to re-initiate the locking sequence when released
power_down Input Power Down: When asserted, places the clocking primitive into low power state, which stops the output clocks
input_clk_stopped Output Input Clock Stopped: When asserted, indicates that the selected input clock is no longer toggling
locked Output Locked: When asserted, indicates that the output clocks are stable and usable by downstream circuitry
locked_fb Output Locked_fb: When asserted, indicates that the feedback clock is stable.
s_axi_* Input/Output See Appendix A of the Vivado Design Suite: AXI Reference Guide (UG1037). This signal is available only if dynamic reconfiguration is enabled.
locked_deskew1 Output Locked_DESKEW1: When asserted, indicates that the DESKEW PD1 Network clocks are stable.
locked_deskew2 Output Locked_DESKEW2: When asserted, indicates that the DESKEW PD2 Network clocks are stable.
clkfb_stopped Output CLKFBStopped: It is asserted when the feedback clock is lost.
interrupt Output Interrupt: This port is available when clock monitor is selected. This port gives the interrupts of the clock monitor feature
clk_oor [3:0] Output clk_OOR: This port is available when clock monitor is selected. The bits for this port are high when input clock frequency is out of range than expected.
  • Bit 0 - User clock 0
  • Bit 1 - User clock 1
  • Bit 2 - User clock 2
  • Bit 3 - User clock 3
clk_glitch [3:0] Output clk_glitch: This port is available when clock monitor is selected. The bits for this port are high when there is a glitch in the input clock.
  • Bit 0 - User clock 0
  • Bit 1 - User clock 1
  • Bit 2 - User clock 2
  • Bit 3 - User clock 3
clk_stop [3:0] Output clk_stop: This port is available when clock monitor is selected. The bits for this port are high when clock is stopped on the respective user clock. clock is stopped
  • Bit 0 - User clock 0
  • Bit 1 - User clock 1
  • Bit 2 - User clock 2
  • Bit 3 - User clock 3
Note: Exposure of every status and control port is individually selectable. To enable interrupt register, you must write to the interrupt enable register with all 1's. This allows you to enable interrupt for clock stop, clock overrun, and clock underrun bits in the interrupt status register.