•Supports 3GPP TS 38.212 V15.1.1 3rd Generation Partnership Project; Technical Specification Group Radio Access Network; NR; Multiplexing and channel coding (Release 15)
•Polar encode or decode
•Throughput(1) up to:
°>80 Mb/s for decoder (N=1024, K=200)
°>700 Mb/s for encoder (N=1024, K=200)
•High bandwidth AXI4-Stream interfaces
1.See performance in the Polar Encoder/Decoder Product Guide (PG280). Figures are for a clock frequency of 400 MHz and should be scaled for achieved clock frequency. Throughput is a function of many factors including code size, code mix, clock frequency and augmentation parameters
LogiCORE IP Facts Table |
|
---|---|
Core Specifics |
|
Supported Device Family(1) |
Versal® ACAP UltraScale™, UltraScale+™ 7 Series |
Supported User Interfaces |
AXI4-Lite, AXI4-Stream |
Provided with Core |
|
Design Files |
N/A |
Example Design |
IP Integrator Block Diagram |
Test Bench |
Verilog |
Constraints File |
Xilinx Design Constraints (XDC) |
Simulation Model |
System Verilog Secure model MEX file for use with MATLAB |
Supported |
Standalone |
Tested Design Flows(2) |
|
Design Entry |
Vivado® Design Suite |
Simulation |
For supported simulators, see the |
Synthesis |
Vivado |
Support |
|
Release Notes and Known Issues |
Master Answer Record: 70106 |
All Vivado IP Change Logs |
Master Vivado IP Change Logs: 72775 |
Notes: 1.For a complete listing of supported devices, see the Vivado IP catalog. 2.For the supported versions of the tools, see the Xilinx Design Tools: Release Notes Guide. 3.The Early Access version of this core only supports Mentor Graphics Questa Advanced Simulator v10.5c |