Table: Core Clocks
provides details about the core clocks.
Table A-3:
Core Clocks
Clock
|
Frequency
|
IP
Configuration
|
Notes
|
drpclk_in
|
100.0 MHz
(Default)
|
All
|
DRPCLK frequency value valid range differs for given device. See the respective data sheets for the clock range (FGTHDRPCLK for GTH transceiver).
|
rxoutclk
|
148.5 MHz for integer SDI line rate
148.35 MHz for fractional SDI line rate
|
All
|
RXOUTCLK clock from serial transceiver
|
BUFG_I
(txoutclk)
|
148.5 MHz for integer SDI line rate
148.35 MHz for fractional SDI line rate
|
All
|
TXOUTCLK clock from serial transceiver.
Connected to BUFG/BUFH/BUFR.
|