The subsystem has three reset ports:
• s_axi_arstn: Active-Low reset for the AXI4-Lite register interface and synchronous with s_axi_aclk .
• video_in_arstn: Active-Low reset for the subsystem blocks and synchronous with video_in_clk .
• sdi_tx_rst: Active-High reset for the SMPTE UHD-SDI TX core and synchronous with sdi_tx_clk . See the Clocking section the SMPTE UHD-SDI Product Guide [Ref 6] .
Table: Core Resets summarizes all resets available to the SMPTE UHD-SDI TX Subsystem and the components affected by them.
Note: The effect of each reset ( s_axi_arstn , video_in_arstn , sdi_tx_rst ) is determined by the ports of the sub-cores to which they are connected. See the individual sub-core product guides for the effect of each reset signal. All the resets should be active until the associated clocks are stable.