Most clocks enter the device through a global clock-capable I/O (GCIO) pin. In horizontal XPIO banks, these clocks directly drive the clock network via a global clock buffer or are transformed by an MMCM, XPLL, or DPLL located in the clock management tiles (CMTs) of the XPIO bank. For devices with columnar HDIO banks, the clocks drive the clock network via a global clock buffer or are transformed by DPLL located in the CMT of the HDIO bank for devices with this feature.
Each horizontal XPIO bank contains the following clocking resources:
- Clock generation blocks
- 1 MCMM
- 2 XPLLs
- 1 DPLL
- Global clock buffers
- 24 BUFGCEs/MBUFGCEs
- 8 BUFGCTRLs/MBUFGCTRLs
- 4 BUFGCE_DIVs/MBUFGCE_DIVs
For devices with columnar HDIO banks, each bank contains the following clocking resources:
- Clock generation blocks
- 1 DPLL
- Global clock buffers
- 4 BUFGCEs/MBUFGCEs
Each gigabit transceiver (GT*_QUAD) clock region column contains the following clocking resources:
- Clock generation blocks
- 1 DPLL
- Global clock buffers
- 24 BUFG_GTs/MBUFG_GTs
Following is summary information for each of the Versal device clock buffers:
- BUFGCE
- The most commonly used buffer is the BUFGCE. This is a general clock buffer with a clock enable/disable feature.
- MBUFGCE
- The MBUFGCE is useful when simple division of the clock is required and uses leaf-level division. The leaf-level division results in less clock track resource utilization, improved power efficiency, and improved skew between synchronous clock domains.
- BUFGCE_DIV
- The BUFGCE_DIV is useful when a simple division of the clock is required. It is considered easier to use and more power efficient than using an MMCM or PLL for simple clock division.
- MBUFGCE_DIV
- The MBUFGCE_DIV is useful when a simple division of the clock is required and uses leaf-level division. The leaf-level division results in less clock track resource utilization, improved power efficiency, and improved skew between synchronous clock domains.
- BUFGCTRL (also BUFGMUX)
- The BUFGCTRL can be instantiated as a BUFGMUX and is generally used when multiplexing two or more clock sources to a single clock network. As with the BUFGCE and BUFGCE_DIV, this clock buffer can drive the clock network for either regional or global clocking.
- MBUFGCTRL
- The MBUFGCTRL is useful when controlling two or more clock sources and when simple division of the output clock is required. The MBUFGCTRL uses leaf-level division that results in less clock track resource utilization, improved power efficiency, and improved skew between synchronous clock domains.
- BUFG_GT
- When using clocks generated by GTs, the BUFG_GT clock buffer allows connectivity to the global clock network. In most cases, the BUFG_GT is used as a regional buffer with its loads placed in one or two adjacent clock regions. The BUFG_GT has built-in dynamic clock division capability that you can use in place of an MMCM for clock rate changes.
- MBUFG_GT
- The MBUFG_GT is useful when driving the global clock network from clock generated by GTs and when simple division of the output clock is required. The MBUFG_GT uses leaf-level division that results in less clock track resource utilization, improved power efficiency, and improved skew between synchronous clock domains.
- BUFG_PS
- The BUFG_PS is a simple clock buffer with one clock input (I) and one clock output (O). This clock buffer is a resource for the PS and provides access to the PL clock routing resources for clocks from the processor into the PL. There are up to 12 BUFG_PS buffers available. This clock buffer resides in the vertical clocking column next to the PS.
- MBUFG_PS
- This primitive is designed as a multi-output high fanout buffer for low skew distribution of the PS clock signals.
- BUFG_FABRIC
- The BUFG_FABRIC is driven by the PL and used for routing high fanout non-clock nets. It allows you to bring a signal from PL routing resources onto the clock network. However, it is not for global clocking.
MBUFGs are clocking primitives that allow you to take advantage of the leaf-level clock dividers driven by the local horizontal clock distribution tracks in Versal devices. The MBUFG primitives (MBUFGCE, MBUFGCE_DIV, MBUFG_GT, MBUFGCTRL and MBUFG_PS) have four outputs (O1, O2, O3, O4) that configure a clock divider setting of 1, 2, 4, and 8, respectively, for any leaf clock divider driving the clocking loads connected to the MBUFG primitive. This results in the use of only one global clock routing resource for all clock loads driven by the MBUFG. For more information on how the MBUFG primitives can help to reduce the high skew between synchronous clock domains, see this link in the Versal ACAP System Integration and Validation Methodology Guide (UG1388).
To use the MBUFG primitives in your design instead of the standard BUFG primitives, select the MBUFG primitives when running the Versal ACAP Clocking Wizard. The MBUFG primitives are only available when the output frequencies are multiple to each other by a factor of 2, 4, or 8. For more information, see this link in the Clocking Wizard for Versal ACAP LogiCORE IP Product Guide (PG321).
opt_design
) to transform some BUFG primitives into MBUFG
primitives. Transformation using opt_design
is only
possible in certain cases and includes some limitations. For more information, see the
Vivado Design Suite User Guide:
Implementation (UG904).The following figure shows logical and physical implementation views of a MBUFG-driven clocking network. The BUFDIV_LEAF primitives are not represented in the logical netlist but are route-through primitives that are configured by the Vivado router. The CLRB_LEAF input on the MBUFG primitives can be used to asynchronously reset the BUFDIV_LEAF dividers. A signal connected to the MBUFG CLRB_LEAF pin is automatically routed to its connected BUFDIV_LEAF CLR_B pin. Because only the 1x clock is routed on the global clock routing and distribution tracks, MBUFG-driven clocks preserve clocking resources. In addition, the common node for paths that are clocked by two output clocks of the same MBUFG is typically much closer to the driver and the load, reducing clock skew and increasing performance.
On device startup, the BUFDIV_LEAF clock dividers are reset, and the MBUFG output clocks start up in the High state. In the following cases, special handling is required to ensure that the BUFDIV_LEAF dividers are reset to their startup state before the MBUFG receives an input clock or is enabled again:
- If the MBUFG clock buffer or a clock modifying block driving an MBUFG is reset during device operation
- If the MBUFG-driven clock network is part of a reconfigurable partition
To reset the BUFDIV_LEAF buffers, the CLRB_LEAF pin of the MBUFG must be asserted Low. To ensure proper device operation, the user logic must stop the MBUFG clock before the CLRB_LEAF pin is asserted Low and hold the clock inactive for a predetermined amount after the CLRB_LEAF signal is deasserted High. The time to hold the clock inactive after the CLRB_LEAF signal is deasserted must be greater than the maximum pin delay time that the router reports for routing the signal connected to the MBUFG CLRB_LEAF pin to the BUFDIV_LEAF CLR_B pins. The router reports this time in an INFO message as shown in the following example. A 10 ns delay is sufficient in most cases to satisfy the CLRB_LEAF net route delay.
INFO: [Route 35-3345] MBUFG*/CLRB_LEAF net route delay summary. Please ensure that
the wait time between de-asserting the CLRB_LEAF signal to each MBUFG and enabling
the MBUFG output clocks is greater than the delay listed in the table below.
+----------------------+--------------------+----------------------+--------------------+
| MBUFG Cell | Site | CLRB_LEAF Net Name | Max Pin Delay (ns) |
+----------------------+--------------------+----------------------+--------------------+
| U_hwsim_engine/dcm | BUFGCE_DIV_X3Y0 | U_hwsim_engine/p_1 | 2.252 |
| _bufg_fx | | _out | |
+----------------------+--------------------+----------------------+--------------------+
The following figure shows the timing relationship required between the MBUFGCE_DIV CLRB_LEAF and CE signal assertion after CLR has been asserted. The CE signal is held Low to stop the clock until the CLRB_LEAF signal has propagated to all of the BUFDIV_LEAF CLR_B pins. In this example, the CE_TYPE property of the MBUFGCE_DIV is set to SYNC.
You can use the Clock Utilization Report in the Vivado IDE to visually analyze clocking resource utilization and clock routing. The following figure shows the clock resource utilization per clock region overlaid in the Device window. For more information on this report, see the Vivado Design Suite User Guide: Design Analysis and Closure Techniques (UG906).
For more information on the BUFGCE, MBUFGCE, BUFGCE_DIV, BUFGCTRL, and MBUFGCTRL buffers, see the Versal ACAP Clocking Resources Architecture Manual (AM003). For details on connectivity and use of the BUFG_GT and MBUFG_GT buffers, see the Versal ACAP GTY and GTYP Transceivers Architecture Manual (AM002).