SD Card Interface

ZCU111 Evaluation Board User Guide (UG1271)

Document ID
UG1271
Release Date
2023-04-28
Revision
1.4 English

[ This Figure , callout 6]

The ZCU111 board includes a secure digital input/output (SDIO) interface to provide access to general purpose non-volatile SDIO memory cards and devices. Information for the SD I/O card specification can be found at the SanDisk Corporation [Ref 18] or SD Association [Ref 19] websites. The ZCU111 SD card interface supports the SD1_LS configuration boot mode documented in the Zynq UltraScale+ Device Technical Reference Manual (UG1085) [Ref 3] .

The SDIO signals are connected to XCZU28DR RFSoC PS bank 501, which has its VCCMIO set to 1.8V. The six SD interface nets MIOxx_SDIO_DAT[0:3], MIO50_SDIO_CMD, and MIO51_SDAIO_CLK each have a series 30Ω resistor at the bank 501 source. An NXP IP4856CX25 SD 3.0-compliant voltage level-translator U107 is present between the XCZU28DR RFSoC and the SD card connector (J100). The NXP IP4856CX25 U107 device provides SD3.0 capability with SDR104 performance.

This Figure shows the connections of the SD card interface on the ZCU111 board.

Figure 3-7: SD Card Interface

X-Ref Target - Figure 3-7

X20483-sd-card.jpg

The NXP SD3.0 level shifter is mounted on an Aries adapter board that has the pin mapping shown in Table: IP4856CX25 U107 Adapter Pin-Out .

Table 3-12: IP4856CX25 U107 Adapter Pin-Out

Aires Adapter Pin Number

IP4856CX25 U107 Pin Number

IP4856CX25 U107 Pin Name

1

C1

CLK_IN

2

C3

GND

3

D3

CD

4

D2

CMD_H

5

E2

CLK_FB

6

E4

WP

7

B4

VLDO

8

C4

VSD_REF

9

A3

DIR_0

10

A4

VSUPPLY

11

B3

VCCA

12

A2

DIR_CMD

13

D1

DATA0_H

14

B2

SEL

15

B1

DATA3_H

16

E1

DATA1_H

17

E3

DIR_1_3

18

A1

DATA2_H

19

E5

DATA1_SD

20

D5

DATA0_SD

21

C5

CLK_SD

22

D4

CMD_SD

23

B5

DATA3_SD

24

A5

DATA2_SD

25

C2

ENABLE

The connections between the SD NXP IP4856CX25 (U107) level-shifter and the XCZU28DR RFSoC PS bank 501 are referenced in Design Constraints .