MDM Core User-Accessible Debug Registers - 3.2 English

MicroBlaze Debug Module LogiCORE IP Product Guide (PG115)

Document ID: PG115
Release Date: 2021-01-21
Version: 3.2 English

Table 1. MDM Core User-Accessible Debug Registers
Register Name	Size (bits)	MDM Command	DBG_CTRL Value	Access	Description
General
MDM Configuration	32	00001100	0x6181F	R	The MDM configuration.
MDM Extended Configuration	35	00001100	0x61822	R	The MDM extended configuration.
Which MicroBlaze ¹	8-32	00001101	8: 0x61A07 9: 0x61A08 ... 32: 0x61A1F	W	Which MicroBlaze processors to access. This register has a variable bit size.
Cross Trigger Debug Registers (C_USE_CROSS_TRIGGER = 1)
External Cross Trigger Control	10	01000000	0x68009	W	External cross trigger control register, used to set the trigger output source, and trigger input mask for each of the four triggers.
Cross Trigger Control	16	01000110	0x68C0F	W	Cross trigger control register used to set the trigger output source, trigger input mask, and logic function to combine inputs for each of the eight triggers.
Cross Trigger Status	24	01000010	0x68417	R	Cross trigger status register to read the current values of all trigger inputs and outputs.
External Trace Register (C_TRACE_OUTPUT = 1)
External Trace Control	14	01001110	0x69C0D	W	External trace control register, used to control test pattern generation, and trigger output.
AXI4-Stream Trace Register (C_TRACE_OUTPUT = 2)
AXI4-Stream Trace Control	8	01001110	0x69C07	W	AXI4-Stream trace control register, used to set delay between output packets.
AXI4-Master Trace Registers (C_TRACE_OUTPUT = 3)
AXI4-Master Trace Status	3	01001010	0x69402	R	AXI4-Master trace status register, with buffer wrap and bus interface response status.
AXI4-Master Trace Current Address ²	32-64	01001011	0x6961F - 0x6963F	R	AXI4-Master trace current address register, with the current buffer address.
AXI4-Master Trace Low Address³	16-48	01001100	0x6980F - 0x6982F	W	AXI4-Master trace low address register, used to define the buffer low address.
AXI4-Master Trace High Address³	16-48	01001101	0x69A0F - 0x69A2F	W	AXI4-Master trace high address register, used to define the buffer high address.
AXI4-Master Trace Control	1	01001110	0x69C00	W	AXI4-Master trace control register, used to define buffer full behavior.
8 to 32 bits, depending on the number of connected MicroBlaze cores. For fewer than eight cores, the register is 8 bits. The size is determined by the C_M_AXI_ADDR_WIDTH parameter. The size is determined by the C_M_AXI_ADDR_WIDTH parameter subtracted by 16.