Lab 1: Running the Simulator in Vivado IDE - 2022.1 English

Vivado Design Suite Tutorial: Logic Simulation (UG937)

Document ID
UG937
Release Date
2022-05-31
Version
2022.1 English

In this lab, you create a new Vivado® Design Suite project, add HDL design sources, add IP from the Xilinx® IP catalog, and generate IP outputs needed for simulation. Then you run a behavioral simulation on an elaborated RTL design.