Mixed Language Support - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

Mixed Language Support

Introduction

Vivado® synthesis supports VHDL and Verilog mixed language projects except as otherwise noted.

Mixing VHDL and Verilog

The VHDL and Verilog files that make up a project are specified in a unique HDL project file. The rules for mixing VHDL and Verilog are, as follows:

°Mixing VHDL and Verilog is restricted to design unit (cell) instantiation.

°A Verilog module can be instantiated from VHDL code and a VHDL entity can be instantiated from Verilog code. No other mixing between VHDL and Verilog is supported. For example, you cannot embed Verilog source code directly in VHDL source code.

°In a VHDL design, a restricted subset of VHDL types, generics, and ports is allowed on the boundary to a Verilog module. In a Verilog design, a restricted subset of Verilog types, parameters, and ports is allowed on the boundary to a VHDL entity or configuration. See VHDL and Verilog Boundary Rules.

°Vivado synthesis binds VHDL design units to a Verilog module during HDL elaboration.

Instantiation

For instantiation, the following rules apply:

°Component instantiation based on default binding is used for binding Verilog modules to a VHDL design unit.

°For a Verilog module instantiation in VHDL, Vivado synthesis does not support:

-Configuration specification

-Direct instantiation

-Component configurations

Instantiating VHDL in Verilog

To instantiate a VHDL design unit in a Verilog design, do the following:

1.Declare a module name with the same as name as the VHDL entity that you want to instantiate (optionally followed by an architecture name).

2.Perform a normal Verilog instantiation.

Instantiating Verilog in VHDL

To instantiate a Verilog module in a VHDL design, do the following:

1.Declare a VHDL component with the same name as the Verilog module to be instantiated. VHDL direct entity instantiation is not supported when instantiating a Verilog module.

2.Observe case sensitivity.

3.Instantiate the Verilog component as if you were instantiating a VHDL component.

°Binding a component to a specific design unit from a specific library by using a VHDL configuration declaration is not supported. Only the default Verilog module binding is supported.

°The only Verilog construct that can be instantiated in a VHDL design is a Verilog module. No other Verilog constructs are visible to VHDL code.

°During elaboration, Vivado synthesis treats all components subject to default binding as design units with the same name as the corresponding component name.

°During binding, Vivado synthesis treats a component name as a VHDL design unit name and searches for it in the logical library work.

-If Vivado synthesis finds a VHDL design unit, Vivado synthesis binds it.

-If Vivado synthesis does not find a VHDL design unit, it treats the component name as a Verilog module name and searches for it using a case sensitive search. Then Vivado synthesis selects and binds the first Verilog module matching the name.

°Because libraries are unified, a Verilog cell with the same name as a VHDL design unit cannot exist in the same logical library.

°A newly-compiled cell or unit overrides a previously-compiled cell or unit.

Instantiation Limitations

VHDL in Verilog

Vivado synthesis has the following limitations when instantiating a VHDL design unit in a Verilog module:

The only VHDL construct that can be instantiated in a Verilog design is a VHDL entity. No other VHDL constructs are visible to Verilog code. Vivado synthesis uses the entity-architecture pair as the Verilog-VHDL boundary.

Use explicit port association. Specify formal and effective port names in the port map.

All parameters are passed at instantiation, even if they are unchanged.

The override is named and not ordered. The parameter override occurs through instantiation, not through defpas.

Acceptable Example

ff #(.init(2'b01)) u1 (.sel(sel), .din(din), .dout(dout));

Unacceptable Example

ff u1 (.sel(sel), .din(din), .dout(dout));

defpa u1.init = 2'b01;

Verilog in VHDL

Vivado synthesis has the following limitations when instantiating a Verilog module in a VHDL design unit:

Use explicit port association. Specify formal and effective port names in the port map.

All parameters are passed at instantiation, even if they are unchanged.

The parameter override is named and not ordered. The parameter override occurs through instantiation, and not through defpas.

Only component instantiation is supported when instantiating a Verilog module in VHDL. Direct entity instantiation is not supported.

VHDL and Verilog Libraries

For libraries with mixed VHDL and Verilog, libraries are handled as follows:

VHDL and Verilog libraries are logically unified.

The default work directory for compilation is available to both VHDL and Verilog.

Mixed language projects accept a search order for searching unified logical libraries in design units (cells). Vivado synthesis follows this search order during elaboration to select and bind a VHDL entity or a Verilog module to the mixed language project.

VHDL and Verilog Boundary Rules

VHDL and Verilog boundary rules are, as follows:

°The boundary between VHDL and Verilog is enforced at the design unit level.

°A VHDL entity or architecture can instantiate a Verilog module. See Instantiating VHDL in Verilog in the following section.

°A Verilog module can instantiate a VHDL entity. See Instantiating Verilog in VHDL.

Binding

Vivado synthesis performs binding during elaboration. During binding, the following actions occur:

1.Vivado synthesis searches for a Verilog module with the same name as the instantiated module with a user-specified list of unified logical libraries and with a user-specified order.

2.Vivado synthesis ignores any architecture name specified in the module instantiation.

3.If Vivado synthesis finds the Verilog module, synthesis binds the name.

4.If Vivado synthesis does not find the Verilog module, then it treats the Verilog module as a VHDL entity, and searches for the first VHDL entity matching the name using a case sensitive search for a VHDL entity in the user-specified list of unified logical libraries or the user-specified order. This assumes that a VHDL design unit is stored with an extended identifier.

Generics Support

Vivado synthesis supports the following VHDL generic types and their Verilog equivalents for mixed language designs: integer, real, string, boolean.

Port Mapping

Vivado synthesis supports port mapping for VHDL instantiated in Verilog and Verilog instantiated in VHDL.

Port Mapping for VHDL Instantiated in Verilog

When a VHDL entity is instantiated in a Verilog module, formal ports can have the following characteristics:

Allowed directions: in, out, inout

Unsupported directives: buffer, linkage

Allowed data types: bit, bit_vector, std_logic, std_ulogic, std_logic_vector, std_ulogic_vector

Port Mapping for Verilog Instantiated in VHDL

When a Verilog module is instantiated in a VHDL entity or architecture, formal ports can have the following characteristics:

Allowed directions are: input, output, and inout.

Allowed data types are: wire and reg

Vivado synthesis does not support:

°Connection to bidirectional pass options in Verilog.

°Unnamed Verilog ports for mixed language boundaries.

Use an equivalent component declaration to connect to a case sensitive port in a Verilog module. Vivado synthesis assumes Verilog ports are in all lowercase.