Constants - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

SystemVerilog gives three types of elaboration-time constants:

parameter: Is the same as the original Verilog standard and can be used in the same way.

localparameter: Is similar to parameter but cannot be overridden by upper-level modules.

specparam: Is used for specifying delay and timing values; consequently, this value is not supported in Vivado synthesis.

There is also a run-time constant declaration called const.