Operators - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

Vivado synthesis supports the following SystemVerilog operators:

Assignment operators (=, +=, -=, *=, /=, %=, &=, |=, ^=, <<=, >>=, <<<=, >>>=)

Unary operators (+, -, !, ~, &, ~&, |, ~|, ^, ~^, ^~)

Increment/decrement operators (++, --)

Binary operators (+, -, *, /, %, ==, ~=, ===, ~==, &&, ||, **, <, <=, >, >=, &, |, ^, ^~, ~^, >>, <<, >>>, <<<)

Note:   A**B is supported if A is a power of 2 or B is a constant.

Conditional operator (? :)

Concatenation operator ({...})