Variables - 2022.1 English

Vivado Design Suite User Guide: Synthesis (UG901)

Document ID
UG901
Release Date
2022-06-06
Version
2022.1 English

A VHDL variable is:

Declared in a process or a subprogram.

Used within that process or subprogram.

Assigned with the := assignment operator.

variable var1 : std_logic_vector (7 downto 0); var1 := "01010011";