Approach 1: Generate Partial Bitstreams from Full Configurations - 2021.2 English

Vivado Design Suite Tutorial: Dynamic Function eXchange (UG947)
Document ID
UG947
Release Date
2022-04-18
Version
2021.2 English

Using the Abstract Shell approach, you did not create multiple configurations as the standard flow uses, as each RM is implemented on its own, independent of the full static top. However, you can create any possible configuration by linking the original full static checkpoint with one RM checkpoint per RP.

  1. Source this script to create all bit files. In the Tcl Console, make sure you are currently in the level above the project_dfxc_vcu118 directory, where this script exists.

    source create_all_bitstreams_via_configs_vcu118.tcl

    This script first generates full and partial bitstreams from the impl_1 run exactly how it was done for Lab 7. Then, it assembles a “child_0” configuration from the count_down and shift_left RMs implemented within the Abstract Shells before generating their partial bitstreams.

    The linking portion of the script looks like this:

    create_project -in_memory -part $part

    add_files ./project_dfxc_vcu118/project_dfxc_vcu118.runs/impl_1/top_routed_bb.dcp

    add_files ./abstract_shell/abs_shift_left/rm_shift_left_route_design.dcp

    set_property SCOPED_TO_CELLS {inst_shift} [get_files ./abstract_shell/abs_shift_left/rm_shift_left_route_design.dcp]

    add_files ./abstract_shell/abs_count_down/count_down_route_design.dcp

    set_property SCOPED_TO_CELLS {inst_count} [get_files ./abstract_shell/abs_count_down/count_down_route_design.dcp

    link_design -mode default -reconfig_partitions {u_shift u_count} -part $part -top top

    write_checkpoint -force abstract_shell/config_shift_left_count_down_import/top_route_design.dcp

    This configuration is effectively the same as Lab 7 produced for the child_0_impl_1 through the project flow. At this point, you have a full configuration from which you can run write_bitstream in the traditional manner using a non-project approach. This by default will produce all full and partial bitstreams for this design image. You can use the -no_partial_bitfile or -cell options to create only full or only partial bit files, respectively. In this lab, you do not use the full design bitstream from the child implementation.