Some user applications such as video streaming and Ethernet-based applications make use of I/O ports on the platform to stream data into and out of the platform. For these applications, performing software and hardware emulation of the design, or running AI Engine simulation, requires a mechanism to mimic the hardware behavior of the I/O port, and to simulate data traffic running through the ports. I/O traffic generators let you model traffic through the I/O ports during software and hardware emulation in the Vitis application acceleration development flow, during the AI Engine simulation flows (x86sim, aiesim), or during logic simulation in the Vivado Design Suite.
As described in AXI4-Stream I/O Model for Streaming Traffic through Python/C++/Verilog, traffic generators can be written in Python/C/C++ or RTL (Verilog/SV) modules; they are launched in an external process which communicates with Vitis Emulation process or AI Engine simulation process using Inter Process Communication (IPC). The IPC connections are established using IPC AXI4-Stream master/slave modules as described in Running Traffic Generators in Python/C++.
The following are additional details on ways to integrate traffic generators in Python/C/C++/Verilog with subsequent PL kernels or the AI Engine kernels based on your application.