Master Bridge - 3.3 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID

PG347

Release Date

2023-05-16

Version

3.3 English

The master bridge processes both PCIe MemWr and MemRd request TLPs received from the integrated block for PCI Express and provides a means to translate addresses that are mapped within the address for PCIe domain to the memory mapped AXI4 address domain. Each PCIe MemWr request TLP header is used to create an address and qualifiers for the memory mapped AXI4 bus and the associated write data is passed to the addressed memory mapped AXI4 Slave. The Master Bridge can support up to 32 active PCIe MemWr request TLPs. PCIe MemWr request TLPs support is as follows:

Each PCIe MemRd request TLP header is used to create an address and qualifiers for the memory mapped AXI4 bus. Read data is collected from the addressed memory mapped AXI4 bridge slave and used to generate completion TLPs which are then passed to the integrated block for PCI Express. The Master Bridge in AXI Bridge mode can support up to 32 active PCIe MemRd request TLPs with pending completions for improved AXI4 pipe-lining performance.

All AXI4_MM master transfer can be directed to modules based on the QDMA controller selection and the steering selection in the GUI as shown in the following table:

Table 1. Controller Steering Options
Controller	Steering Options
CTRL 0	CPM PCIE NoC 0 CPM PCIE NoC 1 CCI PS AXI 0
CTRL 1	CPM PCIE NoC 0 CPM PCIE NoC 1 CCI PS AXI 0 PL AXI0 PL AXI1

All AXI4_MM master transfer have SMID set to 0.