QDMA_TRQ_MSIX (0x2000) - 3.3 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2023-05-16
Version
3.3 English
Table 1. QDMA_TRQ_MSIX (0x2000)
Byte Offset Bit Default Access Type Field Description
0x2000 [31:0] 0 NA addr MSIX_Vector0_Address[63:32]

MSI-X vector0 message lower address.

0x2004 [31:0] 0 RO addr MSIX_Vector0_Address[63:32]

MSI-X vector0 message upper address.

0x2008 [31:0] 0 RO data MSIX_Vector0_Data[31:0]

MSI-X vector0 message data.

0x200C [31:0] 0 RO control MSIX_Vector0_Control[31:0]

MSI-X vector0 control.

Bit Position:

31:1: Reserved.

0: Mask. When set to 1, this MSI-X vector is not used to generate a message. When reset to 0, this MSI-X vector is used to generate a message.

The MSI-X table PBA offset is at 0x1400.

Note: The table above represents one MSI-X table entry 0. Each function can only support up to 32 vectors.