XDMA Features - 3.3 English

Versal Adaptive SoC CPM DMA and Bridge Mode for PCI Express Product Guide (PG347)

Document ID
PG347
Release Date
2023-05-16
Version
3.3 English
  • 64-bit source, destination, and descriptor addresses.
  • Up to four host-to-card (H2C/Read) data channels.
  • Up to four card-to-host (C2H/Write) data channels.
  • Selectable user interface.
    • Single AXI4 (MM) user interface.
    • AXI4-Stream user interface (each channel has its own AXI4-Stream interface; AXI4-Stream is not available when CPM4 configured for 16 GT/s data rate with x16 lane width).
  • AXI4 Bridge Master interface allows for PCIe traffic to bypass the DMA engine.
  • AXI Slave interface allows access to DMA status registers.
  • Scatter Gather descriptor list supporting unlimited list size.
  • 256 MB max transfer size per descriptor.
  • Legacy, MSI, and MSI-X interrupts.
  • Block fetches of contiguous descriptors.
  • Poll Mode.
  • Descriptor Bypass interface.
  • Arbitrary source and destination address.
  • Parity check or Propagate Parity on DMA AXI interface.