Managing IP Constraints - 2022.2 English

Vivado Design Suite User Guide: Designing with IP (UG896)

Document ID

UG896

Release Date

2022-11-02

Version

2022.2 English

The Vivado IDE manages both user-defined XDC timing and physical constraints for the entire design, as well as for Xilinx IP. It handles the association and the unification of constraints for Xilinx IP instantiated multiple times within a project.

Most IP in the IP catalog deliver IP-specific XDC constraints based on user customization. The constraints delivered by the IP are optimized using the default synthesis settings.

Do not change these settings for any of the IP design runs because you could encounter issues with applying constraints. To take ownership of constraining an IP, disable the XDC file(s) that are delivered with an IP. If you must change the synthesis settings for an IP OOC run, you can use the following set_property command in the Tcl console:

set_property <synthesis_option> <value> [get_runs <ip_name>_synth_1]

Tcl Command Example for Changing Synthesis Run Properties

set_property STEPS.SYNTH.DESIGN.ARGS.FSM_EXTRACTION sequential /
[get_runs <ip_name>_synth_1]

During design synthesis and implementation, the Vivado Design Suite processes the IP-delivered XDC constraints before processing the user-defined constraints, or after, depending on the constraint file.

CAUTION:

If any IP is synthesized in OOC mode, the top level synthesis run infers a black box for these IP. Hence, users will not be able to reference objects such as pins, nets, cells, etc., that are internal to the IP as part of the top level synthesis constraints. During implementation, the netlists from the IP DCPs are linked with the netlist produced when synthesizing the top-level design files, and the Vivado Design Suite resolves the IP black boxes. The IP XDC output products that were generated for use during implementation are applied along with any user constraints.