Traffic Analysis - 2021.1 English

Versal ACAP System and Solution Planning Methodology Guide (UG1504)

Document ID
UG1504
Release Date
2021-07-26
Version
2021.1 English

The Versal ACAP includes a built-in network on chip (NoC) that can connect multiple data sources and traffic from complex I/O subsystems to the memory subsystem. Xilinx highly recommends analyzing the type of traffic expected for the application or system. The nature of the dataflow in the application has widespread implications on the total system bandwidth and performance. This traffic analysis step for your application is manual.