Creating Traffic Generators using System Verilog/Verilog - 2022.2 English

AI Engine Tools and Flows User Guide (UG1076)

Document ID
UG1076
Release Date
2022-10-19
Version
2022.2 English

You can drive traffic from external System Verilog /Verilog traffic generators and test benches to the AI Engine simulator or x86 simulator.

Prior to integrating a traffic generator module, declare the external PLIOs in the graph.

pl_in0 = adf::input_plio::create("in_classifier",adf::plio_32_bits);
out0 = adf::output_plio::create("out_interpolator",adf::plio_32_bits);

To establish the connection between the System Verilog/Verilog traffic generator and the AI Engine graph's external PLIOs, the xtlm_ipc SystemC modules are required.

The external AI Engine wrapper is generated based on the external PLIO declarations in the ADF graph. Follow the steps below to generate this wrapper module for the AI Engine.

  1. Use the following command to perform the ADF graph compilation to generate a scsim_config.json file that resides in the work/config/scsim_config.json directory. This config file contains information on the PLIOs declared in the graph.
    aiecompiler --aiearch=aie --platform=$(PLATFORM) -v -log-level=3 --pl-freq=500 -include=./aie --dataflow --output=graph.json aie/graph.cpp
  2. This config file is passed as an argument to the python script available inside ${XILINX_VITIS}/data/emulation/scripts/gen_aie_wrapper.py to generate the Verilog-based AI Engine wrapper module. For more details on how to generate the AI Engine wrapper module, see External RTL Traffic Generator and AI Engine Simulation in Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).
  3. After generating the AI engine wrapper module, you need to instantiate it in an external test bench to make the connection between the System Verilog/Verilog traffic generator and the AI Engine graph PLIOs. For details on integrating the wrapper module into the external RTL test bench, see Instantiating AI Engine Wrapper in the Test Bench in External RTL Traffic Generator and AI Engine Simulation in Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).

After the connection is established, you can launch the HDL simulation in parallel with aiesimulation or x86 simulator. For details on how to launch the HDL simulation, see Running the RTL Traffic Generator with AI Engine Simulation in Vitis Unified Software Platform Documentation: Application Acceleration Development (UG1393).