| Offset | Access Type | Description |
|---|---|---|
| 0x100 | R/W |
AUX_COMMAND_REGISTER. Initiates AUX channel commands of the specified length. [12] - Address only transfer enable. When this bit is set to 1, the source initiates Address only transfers (STOP is sent after the command). [11:8] - AUX Channel Command.
[3:0] - Specifies the number of bytes to transfer with the current command. The range of the register is 0 to 15 indicating between 1 and 16 bytes of data. |
| 0x104 | WO | AUX_WRITE_FIFO. FIFO containing up to 16 bytes of write data for the current
AUX channel command. [7:0] - AUX Channel byte data. |
| 0x108 | R/W | AUX_ADDRESS. Specifies the address for the current AUX channel
command. [19:0] - 20-bit address for the start of the AUX Channel burst. |
| 0x10C | R/W |
AUX_CLOCK_DIVIDER. Contains the clock divider value for generating the internal 1 MHz clock from the AXI4-Lite host interface clock. The clock divider register provides integer division only and does not support fractional AXI4-Lite clock rates (for example, set to 75 for a 75 MHz AXI4-Lite clock). [15:8] - The number of AXI4-Lite clocks (defined by the AXI4-Lite clock name: s_axi_aclk) equivalent to the recommended width of AUX pulse. Allowable values include: 8, 16, 24, 32, 40, 48, 56, 64, 72, 80 and 88. [7:0] - Clock divider value. From DisplayPort Protocol spec, AUX Pulse Width range = 0.4 to 0.6 µs. For example, for AXI4-Lite clock of 50 MHz (= 20 ns), the filter width, when set to 24, falls in the allowable range as defined by the protocol spec. ((20 × 24 = 480)) Program a value of 24 in this register. |
| 0x110 | RC | TX_USER_FIFO_OVERFLOW. Indicates an overflow in the user FIFO. The event can
occur if the video rate does not match the TU size programming. [0] - FIFO_OVERFLOW_FLAG: 1 indicates that the internal FIFO has detected an overflow condition. This bit clears upon read. |
| 0x130 | RO |
INTERRUPT_SIGNAL_STATE. Contains the raw signal values for those conditions which might cause an interrupt. [3] - REPLY_TIMEOUT: 1 indicates that a reply timeout has occurred. [2] - REPLY_STATE: 1 indicates that a reply is currently being received. [1] - REQUEST_STATE: 1 indicates that a request is currently being sent. [0] - HPD_STATE: Contains the raw state of the HPD pin on the DisplayPort connector. |
| 0x134 | RO | AUX_REPLY_DATA. Maps to the internal FIFO which contains up to 16 bytes of
information received during the AUX channel reply. Reply data is read from the FIFO
starting with byte 0. The number of bytes in the FIFO corresponds to the number of
bytes requested. [7:0] - AUX reply data |
| 0x138 | RO |
AUX_REPLY_CODE. Reply code received from the most recent AUX Channel request. The AUX Reply Code corresponds to the code from the DisplayPort Standard. Note: The core does not retry any commands that were Deferred or Not
Acknowledged.
[3:2]
[1:0]
|
| 0x13C | R/W | AUX_REPLY_COUNT. Provides an internal counter of the number of AUX reply
transactions received on the AUX Channel. Writing to this register clears the
count. [7:0] - Current reply count. |
| 0x140 | RC |
INTERRUPT_STATUS. Source core interrupt status register. A read from this register clears all values. Write operation is illegal and clears the values. [13] - VBLANK_STREAM4: VBlank interrupt of video stream 4. Set when the video stream 4 is in vertical blanking period. Valid only in MST mode. [12] - VBLANK_STREAM3: VBlank interrupt of video stream 3. Set when video stream 3 is in vertical blanking period. Valid only in MST mode. [11] - VBLANK_STREAM2: VBlank interrupt of video stream 2. Set when video stream 2 is in vertical blanking period. Valid only in MST mode. [10] - VBLANK_STREAM1: VBlank interrupt of video stream 1. Set when video stream 1 is in vertical blanking period. [9] - Audio packet ID mismatch interrupt, sets when incoming audio packet ID over AXI4-Stream interface does not match with the info frame packet stream ID. [5] - EXT_PKT_TXD: Extended packet is transmitted and controller is ready to accept new packet. Extended packet address space can also be used to send the audio copy management packet/ISRC packet/VSC packets. [4] - HPD_PULSE_DETECTED: A pulse on the HPD line was detected. The duration of the pulse can be determined by reading 0x150. [3] - REPLY_TIMEOUT: A reply timeout has occurred. [2] - REPLY_RECEIVED: An AUX reply transaction has been detected. [1] - HPD_EVENT: The core has detected the presence of the HPD signal. This interrupt asserts immediately after the detection of HPD and after the loss of HPD for 2 ms. [0] - HPD_IRQ: An IRQ framed with the proper timing on the HPD signal has been detected. |
| 0x144 | R/W |
INTERRUPT_MASK. Masks the specified interrupt sources from asserting the axi_init signal. When set to a 1, the specified interrupt source is masked. This register resets to all 1s at power up. The respective MASK bit controls the assertion of axi_int only and does not affect events updated in the INTERRUPT_STATUS register. [13] - VBLANK_STREAM4: Mask VBlank interrupt of video stream 4. Valid only in MST mode. [12] - VBLANK_STREAM3: Mask VBlank interrupt of video stream 3. Valid only in MST mode. [11] - VBLANK_STREAM2: Mask VBlank interrupt of video stream 2. Valid only in MST mode. [10] - VBLANK_STREAM1: Mask VBlank interrupt of video stream 1. [9] - Mask Audio packet ID mismatch interrupt. [5] - EXT_PKT_TXD: Mask Extended Packet Transmitted interrupt. [4] - HPD_PULSE_DETECTED: Mask HPD Pulse interrupt. [3] - REPLY_TIMEOUT: Mask reply timeout interrupt. [2] - REPLY_RECEIVED: Mask reply received interrupt. [1] - HPD_EVENT: Mask HPD event interrupt. [0] - HPD_IRQ: Mask HPD IRQ interrupt. |
| 0x148 | RO | REPLY_DATA_COUNT. Returns the total number of data bytes actually received
during a transaction. This register does not use the length byte of the transaction
header. [4:0] - Total number of data bytes received during the reply phase of the AUX transaction. |
| 0x14C | RO |
REPLY_STATUS [15:12] - RESERVED [11:4] - REPLY_STATUS_STATE: Internal AUX reply state machine status bits. [3] - REPLY_ERROR: When set to a 1, the AUX reply logic has detected an error in the reply to the most recent AUX transaction. [2] - REQUEST_IN_PROGRESS: The AUX transaction request controller sets this bit to a 1 while actively transmitting a request on the AUX serial bus. The bit is set to 0 when the AUX transaction request controller is idle. [1] - REPLY_IN_PROGRESS: The AUX reply detection logic sets this bit to a 1 while receiving a reply on the AUX serial bus. The bit is 0 otherwise. [0] - REPLY_RECEIVED: This bit is set to 0 when the AUX request controller begins sending bits on the AUX serial bus. The AUX reply controller sets this bit to 1 when a complete and valid reply transaction has been received. |
| 0x150 | RO | HPD_DURATION [15:0] - Duration of the HPD pulse in µs. |
| 0x154 | RO | Free running counter incrementing for every 1 MHz. |