Register Details - 3.0 English

DisplayPort 1.4 TX Subsystem Product Guide (PG299)
Document ID
PG299
Release Date
2022-05-04
Version
3.0 English
Register Offset Access Name Default Value Register Description
0x10 R/W Picture Height 0 [15:0] Holds the value of picture height
0x18 R/W Picture Width 0 [15:0] Holds the value of picture width
0x20 R/W Picture Color format 1

[7:0] Holds the value of color format

8’h1 – For YUV444

8’h3 – For YUV422 / YUV420
0x28 R/W inPixClk 0 [7:0] – Holds the value of number of pixels per clock on the input video streaming interface
0x30 R/W outPixClk 0 [7:0] – Holds the value of number of pixels per clock required on the output video streaming interface
0x38 - - This is out of scope as it is meant for HDMI
0x40 - - This is out of scope as it is meant for HDMI
0x48 R/W inPixDrop 0 [0] – When asserted, pixel drop feature on the input video stream gets enabled. This feature is not used in DisplayPort.
0x50 R/W outPixRepeat 0 [0] – When asserted, pixel repeat feature on the output video stream gets enabled. This feature is not used in DisplaypPort.
Clocking
This IP has only one clock namely ap_clk on which all of the three interfaces (s_axi_ctrl, s_axis_video and m_axis_video) work.
Resets
This IP has an active low reset namely, ap_reset_n which when enabled, puts all the registers in default state.
Programming sequence
  • The IP should be generated with “Convert Samples per clock” feature enabled in GUI so as to support re-mapping between various PPCs.
  • Always program the pic height, width, color format, inPixClk and outPixClk values before inputting the corresponding video streaming data.
Functionality
  • AXIvideo2MultiPixStream: In this first stage of data path, the input AXI video stream data is converted in to multi pixel data basing on the inPixClk value which tells how many pixels are being inputted per input clock.
  • pixClkUpConvert, pixClkDownConvert: The output from the first stage comes to this stage, where appropriate up conversion followed by down conversion takes place to output required PPC.
  • MultiPixStream2AXIvideo: In this final stage, the up and down converted multi pixel stream is again converted to AXI video stream output which is finally mapped to output m_axis_video interface.