This section details the registers available in the DisplayPort 1.4 TX Subsystem. The address map is split into the following regions:
- VTC 0 (Up to 3 for 4 streams in MST)
- DisplayPort TX IP
- HDCP Controller
The address offsets of the helper cores is shown in the following table.
| Helper Core | Address Space | Address Offset |
|---|---|---|
| DisplayPort | 8K | 0x0000_0000 |
| HDCP 1.x Subsystem | 8K | 0x0000_2000 |
| HDCP 2.x Subsystem | 8K | 0x0000_4000 |
| AXI Timer | 4K | 0x0000_6000 |
| Clocking Wizard | 4K | 0x0000_7000 |
| VTC1 | 4K | 0x0000_8000 |
| VTC2 | 4K | 0x0000_9000 |
| VTC3 | 4K | 0x0000_A000 |
| VTC4 | 4K | 0x0000_B000 |
| Dual Splitter | 4K | 0x0000_C000 |