After triggering reset, the PHY waits for the PLLs to lock before any further initialization task that uses a high-speed (controller) clock can commence. The PLL initialization completion status is indicated by the PGSR0.P.LDONE bit. The lock status of individual PLLs is indicated by the bits in Table: PLL Lock Status Bits.
Table 17-11: PLL Lock Status Bits
|
Register
|
Bits
|
Name
|
Description
|
Address
|
|
PGSR0
|
[31]
|
APLOCK
|
AC PLL lock: if set, indicates that the AC PLL has locked.
|
0xFD080030
|
|
DX0GSR0
|
[16]
|
DPLOCK
|
DATX8 PLL lock: if set, indicates that the DATX8 PLL controlling bytes 0 and 1 has locked.
|
0xFD0807E0
|
|
DX2GSR0
|
[16]
|
DPLOCK
|
DATX8 PLL lock: if set, indicates that the DATX8 PLL controlling bytes 2 and 3 has locked.
|
0xFD0809E0
|
|
DX4GSR0
|
[16]
|
DPLOCK
|
DATX8 PLL lock: if set, indicates that the DATX8 PLL controlling bytes 4 and 5 has locked.
|
0xFD080BE0
|
|
DX6GSR0
|
[16]
|
DPLOCK
|
DATX8 PLL lock: if set, indicates that the DATX8 PLL controlling bytes 6 and 7 has locked.
|
0xFD080DE0
|
|
DX8GSR0
|
[16]
|
DPLOCK
|
DATX8 PLL lock: if set, indicates that the DATX8 PLL controlling byte 8 has locked.
|
0xFD080FE0
|
If any PLLs fail to lock, check the integrity of the Vcc_psddr_pll supply. See the UltraScale Architecture PCB Design User Guide (UG583) [Ref 15] to ensure that the guidelines for the Vcc_psddr_pll supply have been followed. Check that the correct memory interface device frequency has been entered in the Zynq UltraScale+ MPSoC DDR configuration page in the Vivado design tools. This number must be set no lower than 166 MHz.