The following steps are used to program the PS-GTR transceiver interface to support the PCI Express protocol. For more information on the PS-GTR transceiver interface, refer to PS-GTR Transceivers.
1.Assign SerDes lanes to the PCIe PHY that presents a PIPE interface to the controller for PCIe.
2.Program SERDES.ICM_CFG0 and SERDES.ICM_CFG1 to support the PCIe protocol lanes as per the requirement (Table: PS-GTR Multiplexer Configuration for PCI Express Lanes).
3.Set the PLL reference clock to 100 MHz: SERDES.PLL_REF_SEL0 = 0x0D