There are eight address translation apertures in each direction namely ingress (PCIe to AXI) and egress (AXI to PCIe). Each aperture defines registers for translation that are listed in Table: Ingress Address Translation Registers and Table: Egress Address Translation Registers. The first translation aperture starts at offset 0x00, the next one at 0x20, and the subsequent one at 0x40, and so on.
Table 30-12: Ingress Address Translation Registers
Register Name
|
Description
|
TRAN_INGRESS_CAPABILITIES
|
Ingress AXI translation: capabilities.
|
TRAN_INGRESS_STATUS
|
Ingress AXI translation: status.
|
TRAN_INGRESS_CONTROL
|
Ingress AXI translation: control.
|
TRAN_INGRESS_SRC_BASE_LO
|
Ingress AXI translation: source address Low.
|
TRAN_INGRESS_SRC_BASE_HI
|
Ingress AXI translation: source address High.
|
TRAN_INGRESS_DST_BASE_LO
|
Ingress AXI translation: destination address Low.
|
TRAN_INGRESS_DST_BASE_HI
|
Ingress AXI translation: destination address High.
|
Table 30-13: Egress Address Translation Registers
Register Name
|
Description
|
TRAN_EGRESS_CAPABILITIES
|
Egress AXI translation: capabilities.
|
TRAN_EGRESS_STATUS
|
Egress AXI translation: status.
|
TRAN_EGRESS_CONTROL
|
Egress AXI translation: control.
|
TRAN_EGRESS_SRC_BASE_LO
|
Egress AXI translation: source address Low.
|
TRAN_EGRESS_SRC_BASE_HI
|
Egress AXI translation: source address High.
|
TRAN_EGRESS_DST_BASE_LO
|
Egress AXI translation: destination address Low.
|
TRAN_EGRESS_DST_BASE_HI
|
Egress AXI translation: destination address High.
|