All of the CAN interrupts are sticky. CAN status and interrupts are identified in Table: List of CAN Status and Interrupts. All bits are cleared by writing to the ICR register. Some bits can be cleared by writing a 0 to the can.SRR [CEN] bit field.
Table 20-4: List of CAN Status and Interrupts
Name
|
Bit Number
|
Additional Methods to Clear Interrupt
|
Usage
|
Arbitration lost
|
0
|
Write 0 to can.SRR[CEN]
|
Arbitration lost during message transmission
|
Message TX
|
1
|
Write 0 to can.SRR[CEN]
|
Message transmission successful
|
TXFIFO full
|
2
|
None
|
Read to determine if more TX messages can be written to the TXFIFO.
|
TXHPB full
|
3
|
None
|
Read to determine if more TX messages can be written to the TXHPB.
|
Message RX
|
4
|
Write 0 to can.SRR[CEN]
|
New message received in RXFIFO
|
RXFIFO underflow
|
5
|
None
|
Programming error, message read from RXFIFO when no messages were there.
|
RXFIFO overflow
|
6
|
Write 0 to can.SRR[CEN]
|
RX FIFO was full and RX message(s) likely lost.
|
RXFIFO not empty
|
7
|
None
|
One or more RX messages can be read.
|
Message error
|
8
|
Write 0 to can.SRR[CEN]
|
Any of the five errors in the error status register, ESR.
|
Bus-off state
|
9
|
Write 0 to can.SRR[CEN]
|
Bit is asserted when controller enters bus-off state
|
Enter sleep mode
|
10
|
Write 0 to can.SRR[CEN]
|
Bit is asserted when controller enters sleep state
|
Exit sleep mode
|
11
|
Write 0 to can.SRR[CEN]
|
Controller wakes up and enters normal or configuration mode.
|
RXFIFO watermark
|
12
|
None
|
Operational threshold indicates RXFIFO is above watermark setting.
|
TXFIFO watermark
|
13
|
None
|
Operational threshold indicates TXFIFO has more room than watermark setting.
|
TXFIFO empty
|
14
|
None
|
TXFIFO empty indicator.
|