There are two status registers that can be read by software. Both show raw status. The Chnl_int_sts register can be read for status and generate an interrupt. The Channel_sts register can only be read for status.
The Chnl_int_sts register is sticky; once a bit is set, the bit stays set until software clears it. Write a 1 to clear a bit. This register is bit-wise AND'ed with the Intrpt_mask mask register. If any of the bit-wise AND functions have a result = 1, then the UART interrupt is asserted to the PS interrupt controller.
•Channel_sts: Read-only raw status. Writes are ignored.
The various FIFO and system indicators are routed to the uart.Channel_sts register and/or the uart.Chnl_int_sts register as shown in This Figure.
The interrupt registers and bit fields are summarized in Table: UART Interrupt Status Bits.