The instruction register allows instructions to be entered serially into the PS TAP controller during the Shift-IR state. Table: PS TAP Controller Instructions lists the PS TAP instructions.
HEX Code |
Instruction |
Description |
---|---|---|
0x00 |
Reserved |
Reserved. |
0x03 |
PMU_MDM |
Access the PMU MicroBlaze MDM Security gate must allow access [ssss_pmu_sec]. |
0x08 |
USERCODE |
Access the USERCODE. |
0x09 |
IDCODE |
Access the IDCODE, see Table: Device ID Codes and Minimum Production Revisions. |
0x0A |
HIGHZ |
Allows the GTS_USR_B signal from PL TAP controller to enter the PS. |
0x19 |
IP_DISABLE |
IP disable status register. |
0x1F |
JTAG_STATUS |
JTAG status register read. |
0x20 |
JTAG_CTRL |
Connect/disconnect the PL TAP and Arm DAP. |
0x26 |
EXTEST |
Asserts the bscan_extest signal in the PS. |
0x3E |
ERROR_STATUS |
ERROR status register read (46-bit from PMU). |
0x3F |
BYPASS |
|
The PL TAP and PS TAP instruction registers are 6-bits each. If the PS TAP is not part of the JTAG chain, the last six bits of the instruction register are dummy bits. The DAP controller is daisy chained to the end of the JTAG when it is activated in the system.