DisplayPort Controller Clocking

Zynq UltraScale+ Device Technical Reference Manual (UG1085)

Document ID

UG1085

Release Date

2023-12-21

Revision

2.4 English

The DisplayPort controller operates in different clock domains. Table: DisplayPort Controller Clock Domains summarizes the clocks.

Table 33-12: DisplayPort Controller Clock Domains
Interface/Block Name	Clock(s)
DPDMA to A/V manager	AXI4 memory mapped clock
Live video and graphics	Live video clock
Live audio	Live audio clock
A/V manager	Video master clock, APB clock, audio clock
Video rendering pipe	Video master clock, APB clock
Audio mixer	Audio clock, APB clock
DisplayPort source controller	Video master clock, audio clock, link layer clock.
Live video output	Live video clock
Live audio output	Live audio clock

This Figure shows the clock domains used in the controller.

Figure 33-17: Block Level Clocking
X-Ref Target - Figure 33-17