The transmit module removes parallel data from the TxFIFO and loads it into the transmitter shift register so that it can be serialized.
The transmit module shifts out the start bit, data bits, parity bit, and stop bits as a serial data stream. Data is transmitted, least significant bit first, on the falling edge of the transmit baud clock enable (baud_tx_rate). A typical transmitted data stream is illustrated in This Figure.
The uart.mode[CHRL] register bit selects the character length, in terms of the number of data bits. The uart.mode[NBSTOP] register bit selects the number of stop bits to transmit.