For pin planning, see Table: MIO Interfaces. MIO signals are also listed in each controller chapter along with their function, direction, and presence in EMIO.
|
Interface |
0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
26 |
27 |
28 |
29 |
30 |
31 |
32 |
33 |
34 |
35 |
36 |
37 |
38 |
39 |
40 |
41 |
42 |
43 |
44 |
45 |
46 |
47 |
48 |
49 |
50 |
51 |
52 |
53 |
54 |
55 |
56 |
57 |
58 |
59 |
60 |
61 |
62 |
63 |
64 |
65 |
66 |
67 |
68 |
69 |
70 |
71 |
72 |
73 |
74 |
75 |
76 |
77 |
|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|---|
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gem0 |
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0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
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gem1 |
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0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
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gem2 |
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0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
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gem3 |
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0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
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gem_tsu |
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0 |
0 |
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|
qspi(2) |
4 |
1 |
2 |
3 |
0 |
5 |
12 |
6 |
8 |
9 |
10 |
11 |
7 |
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nand |
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2 |
13 |
14 |
4 |
1 |
3 |
0 |
5 |
6 |
7 |
8 |
9 |
10 |
16 |
11 |
12 |
15 |
2 |
13 |
14 |
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4 |
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|
pcie(3) |
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0 |
0 |
0 |
|
0 |
0 |
0 |
0 |
0 |
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usb0 |
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0 |
1 |
6 |
3 |
4 |
5 |
2 |
7 |
8 |
9 |
10 |
11 |
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usb1 |
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0 |
1 |
6 |
3 |
4 |
5 |
2 |
7 |
8 |
9 |
10 |
11 |
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pmu |
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0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
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|
sd0(1) |
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|
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
3 |
2 |
13 |
1 |
0 |
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|
2 |
1 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
13 |
0 |
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2 |
1 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
13 |
0 |
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|
sd1(1) |
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8 |
9 |
10 |
11 |
13 |
0 |
1 |
4 |
5 |
6 |
7 |
3 |
2 |
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0 |
13 |
4 |
5 |
6 |
7 |
3 |
2 |
1 |
|
CSU tamper |
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0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
0 |
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0 |
0 |
0 |
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DisplayPort aux |
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0 |
1 |
2 |
3 |
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0 |
1 |
2 |
3 |
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gpio0 |
0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
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gpio1 |
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0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
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gpio2 |
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0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
18 |
19 |
20 |
21 |
22 |
23 |
24 |
25 |
|
can0 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
|
can1 |
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
|
1 |
0 |
|
i2c0 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
|
i2c1 |
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
pjtag |
3 |
0 |
1 |
2 |
|
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|
3 |
0 |
1 |
2 |
|
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|
3 |
0 |
1 |
2 |
|
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|
3 |
0 |
1 |
2 |
|
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|
3 |
0 |
1 |
2 |
|
|
3 |
0 |
1 |
2 |
|
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|
lpd_swdt |
|
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|
|
0 |
1 |
|
|
0 |
1 |
|
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|
|
|
0 |
1 |
|
|
0 |
1 |
|
|
|
|
|
|
0 |
1 |
|
|
0 |
1 |
|
|
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|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
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|
|
|
|
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
|
fpd_swdt |
|
|
|
|
0 |
1 |
|
|
0 |
1 |
|
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|
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
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|
|
|
|
0 |
1 |
|
|
0 |
1 |
|
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|
0 |
1 |
|
|
0 |
1 |
|
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|
0 |
1 |
|
|
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|
|
|
0 |
1 |
|
|
0 |
1 |
|
|
0 |
1 |
|
|
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|
spi0 |
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
|
|
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
|
|
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
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|
spi1 |
|
|
|
|
|
|
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
1 |
4 |
3 |
2 |
5 |
0 |
|
|
|
|
|
|
|
|
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
|
|
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
|
|
|
5 |
4 |
3 |
2 |
1 |
0 |
|
|
|
ttc0 |
|
|
|
|
|
|
0 |
1 |
|
|
|
|
|
|
0 |
1 |
|
|
|
|
|
|
0 |
1 |
|
|
|
|
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|
0 |
1 |
|
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|
0 |
1 |
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|
0 |
1 |
|
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|
0 |
1 |
|
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|
0 |
1 |
|
|
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|
|
|
0 |
1 |
|
|
|
|
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|
|
ttc1 |
|
|
|
|
0 |
1 |
|
|
|
|
|
|
0 |
1 |
|
|
|
|
|
|
0 |
1 |
|
|
|
|
|
|
0 |
1 |
|
|
|
|
|
|
0 |
1 |
|
|
|
|
|
|
0 |
1 |
|
|
|
|
|
|
0 |
1 |
|
|
|
|
|
|
0 |
1 |
|
|
|
|
|
|
0 |
1 |
|
|
|
|
|
|
|
|
|
ttc2 |
|
|
0 |
1 |
|
|
|
|
|
|
0 |
1 |
|
|
|
|
|
|
0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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ttc3 |
0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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mdio{0:3} |
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0 |
1 |
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0 |
1 |
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ua0 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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0 |
1 |
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ua1 |
1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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1 |
0 |
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trace |
0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
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6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
0 |
1 |
2 |
3 |
4 |
5 |
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0 |
1 |
2 |
3 |
4 |
5 |
6 |
7 |
8 |
9 |
10 |
11 |
12 |
13 |
14 |
15 |
16 |
17 |
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Notes: 1.SD0/1 peripheral pins can also be configured as eMMC 0/1, respectively. The difference between SD and eMMC configuration is as follows. °The Card Detect and Write Protect signals are only available in SD mode. °The BUS_POW pin in SD mode is treated as a reset pin in eMMC mode. °In SD mode, data transfers in 1-bit and 4-bit modes. In eMMC mode, data transfers in 1-bit, 4-bit, and 8-bit modes. °If the SD interface is configured for SD 3.0, the signals SEL, DIR_CMD, DIR_0, and DIR_1_3 are mapped to sdio{0,1}_data_out [4], [5], [6], and [7], respectively. 2.In Quad-SPI loopback mode, leave the clk_for_lpbk signal floating. In Quad-SPI non-loopback mode, the clk_for_lpbk signal is not used by the Quad-SPI and can be used as a peripheral I/O (such as GPIO, CAN, or I2C). 3.The PCIe Root Port mode reset signals are routed to specific MIO pins as listed in Table: PCIe Reset Signals on MIO. |
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