In scenarios where the AXI interconnect in the PL does not support ACE, all ACE accesses go to the system cache using a point-to-point interface instead of an AXI-ACE interconnect. System cache uses block RAM in the PL to implement the memory cells of cache.
This Figure shows an example of the PL accelerator implementation with system cache using ACE. The PL accelerator can write the data into system cache and the APU can access the same data through ACE. This improves APU performance (as read latency is reduced when compared to reading from DDR) and reduces the DDR bandwidth requirement as DDR access is reduced.
