The security profile for master and slaves are listed in Table: TrustZone Profile.
Module Name |
Registers |
Description |
---|---|---|
CCI_REG |
Controls for the register block |
|
Interrupt Status Register |
||
Interrupt Mask Register |
||
IER_0 |
Interrupt Enable Register |
|
IDR_0 |
Interrupt Disable Register |
|
CCI_MISC_CTRL |
Misc. Control Register |
|
CCI_GPV (CCI 400) |
Control_Override_Register |
Additional control register that provides a fail-safe override for some CCI-400 functions. |
Speculation_Control_Register |
Disables speculative fetches for a master interface or for traffic through a specific slave interface. |
|
Secure_Access_Register |
Secure_Access_Control, Enable non-secure access to CCI-400 registers |
|
Status_Register |
Safely enables and disables snooping |
|
Imprecise_Error_Register |
Records the CCI-400 interfaces that receive an error that is not signaled precisely. |
|
Controls the performance monitor. |
||
Snoop_Control_Register_S0/S1/S2/S3/S4 |
One Snoop Control Register exists for each slave interface. |
|
Shareable_Override_Register_S0/S1/S2/S3 |
Overrides shareability of normal transactions |
|
Read_Qos_OverCCride_Register_S0/S1/S2/S3/S4 |
Contains override values for ARQOS, with a register for each slave interface. |
|
Write_Qos_Override_Register_S0/S1/S2/S3/S4 |
Contains override values for AWQOS, with a register for each slave interface. |
|
Qos_Control_Register_S0/S1/S2/S3/S4 |
Controls the regulators that are enabled on the slave interfaces. |
|
Max_OT_Register_S0/S1/S2 |
Determine how many outstanding transactions are permitted when the OT regulator is enabled for each ACE-Lite slave interface. |
|
Target_Latency_Register_S0/S1/S2/S3/S4 |
Determine the target latency, in cycles, for the regulation of reads and writes. |
|
Latency_Regulation_Register_S0/S1/S2/S3/S4 |
Latency regulation value, AWQOS or ARQOS, scale factor coded for powers of 2 in the range 2-5-2-12, to match a 16-bit integrator. |
|
CCI_GPV (CCI 400) (Cont’d) |
Qos_Range_Register_S0/S1/S2/S3/S4 |
Enables you to program the minimum and maximum values for the ARQOS and AWQOS signals that the QV regulators generate. |
Cycle_Counter |
The cycle counter counts either every CCI-400 clock cycle depending on the PMCR bit. |
|
Cycle_Counter_Control |
Enable or disable the cycle and event counters. |
|
Cycle_Count_Overflow |
Detects for an overflow of the event counter. |
|
Event_Select_Register_0/1/2/3 Selects the event. |
|
|
ESR0/1/2/3 |
|
|
Event_Counter0/1/2/3 |
|
|
|
||
|
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Event_Counter_0/1/2/3 |
Indicates the number of events occur. |
|
Event_Counter_0/1/2/3_Control |
Enables or disables the event counter. |
|
Event_Counter_0/1/2/3_Overflow |
Detects for overflow of the event counter. |