The AXI FIFO interface (AFI) is included to provide high-throughput datapaths between the PL masters and the PS DDR Memory Controller.
•The access latency through the multi-ported DDR memory controller in the PS is expected to vary across a wide range and can vary under loaded conditions. The AXI FIFO interface helps to smooth out this variable latency, allowing the ability to stream data continuously between the DDR and corresponding PL master.
•This module also helps provide rate adjustment between the PL and PS clock domains.
•The PL interface is AXI4 while the PS interface is AXI3-compliant. The AFI converts between AXI4 and AXI3 formats.
The block diagram in This Figure shows the AXI FIFO interface. There are two sets of AXI ports, one set connecting directly to the PL (blue) and the other (PS) connecting to the AXI switch matrix (red), providing access to the PS DDR memory and other slaves.
TIP: The 32, 64, and 128-bit programmable logic interfaces are programmable; the PS-side AXI interface is always 128 bits.
The level of the data FIFOs as well as the command queues for both read and write are exported to the PL, to provide visibility to programmable logic applications.
TIP: The FIFO levels should be used as a relative level as opposed to an exact level, because clock domain crossings are involved; that is, the read and write FIFO levels indicate a pessimistic count of read/write data words when the FIFO interfaces are operating at an asynchronous clock frequency and do not represent the actual words stored in the FIFO.