The device resets are summarized in Table: Resets.
Reset Name |
Source |
Control |
System Effects(1) |
Subject to the PROG_GATE effect for PL? |
Reset Reason |
---|---|---|---|---|---|
External POR |
PS_POR_B pin |
Deasserted after power up. Assert at any time with immediate affect. |
Resets all logic, RAMs, and registers. Prepares device for possible secure boot. •Mode pins sampled. |
No |
[external_por] |
Internal POR |
System error |
PMU_Global.ERROR_POR_{1,2}. |
Same as External POR except: •ERROR_STATUS_{1, 2} registers unaffected. |
No |
[internal_por] |
External SRST |
PS_SRST_B pin(2) |
Device pin that is usually connected to the debugging tool. |
Same as External POR except: •System error enable. •PMU global persistent. •CSU_status, ENC_status •LOC_PWR_STATE (power state). •RAMs not cleared. |
Yes |
[srst] |
Internal SRST |
Register write |
CRL_APB.RESET_CTRL [soft_reset]. |
Same as external SRST. |
Yes |
[soft] |
System error |
PMU_GLOBAL.ERROR_SRST_{1,2}. |
Same as external SRST. |
Yes |
[pmu_sys_reset] |
|
Register write |
CRL_APB.RST_LPD_TOP [fpd_reset]. |
Same as external SRST except: •PL and LPD unaffected. |
N/A |
|
|
Register write |
PMU_GLOBAL.GLOBAL_RESET [PS_ONLY_RST]. |
Same as external SRST except: •PL and LPD unaffected. |
Yes |
[psonly_reset_req] |
|
Debug SRST |
DAP controller |
Arm DAP. |
Same as external SRST except the debug logic state is preserved.(3) |
Yes |
[debug_sys] |
Reset Debugger |
DAP controller |
BLOCKONLY_RST [debug_only]. |
Resets the CoreSight debug logic only. |
N/A |
No change. |
Notes: 1.All resets have an immediate effect. Effects are driven by reset edges and levels. 2.The PS_SRST_B pin can be enabled and disabled by writing to the CRL_APB.RESET_CTRL [srst_dis] bit. |