Trace debug is a non-invasive debug with the processor running at full speed.
•A collection of information on instruction execution and data transfers.
•Delivery off-chip in real-time, or capture in on-chip memory.
•Tools to merge data with source code on a development workstation for future analysis.
•The TPIU.EXTCTL_OUT_Port register must be set to output trace into the PL.
CoreSight technology addresses the requirement for a multi-processor debug and trace solution with high bandwidth for entire systems beyond the processor, despite increased complexity and clock speeds. Efficient use of pins made available for debug is crucial.
The entire CoreSight debug circuit is distributed across the low and full-power domains. Between these two domains, the low-power domain is the always-on power domain. To support RPU MPCore debug in low-power mode, and minimize CoreSight power, the key top-level debug components are allocated in the LPD.
For further information, see the CoreSight on-chip trace and debug [Ref 53] documentation.