The remaining write-protected registers are listed in Table: Write-Protected Registers, Others. The protection is controlled by the lock bit shown in Table: Write-Protected Registers, Others.
Table 16-16: Write-Protected Registers, Others
Register Set
|
Registers
|
Count
|
Lock Register Bit
|
DDR_XMPU{0:5}_CFG
|
ctrl, poison, err_status{1,2}
|
24
|
LOCK [RegWrDis] All registers except interrupt registers.
|
r{00:15}_config, master
|
192
|
r{00:15}_start, end
|
192
|
FPD_XMPU_CFG
|
ctrl, poison, err_status{1,2}
|
4
|
LOCK [RegWrDis] All registers except interrupt registers.
|
r{00:15}_config, master
|
32
|
r{00:15}_start, end
|
32
|
OCM_XMPU_CFG
|
ctrl, poison, err_status{1,2}
|
4
|
LOCK [RegWrDis]
All registers except interrupt registers.
|
r{00:15}_config, master
|
32
|
r{00:15}_start, end
|
32
|
VCU_SLCR
|
alg_{dec,enc}_core_ctrl
|
2
|
CRL_WPROT [ACTIVE] Write lock for several registers.
|
alg_{dec,enc}_mcu_ctrl
|
2
|
alg_vcu_axi_ctrl, pll_status
|
2
|
vcu_pll_{cfg,ctrl}, vcu_pll_frac_cfg
|
2
|
EFUSE
|
efuse_cache_load
|
1
|
WR_LOCK [LOCK] Write lock for several registers.
|
efuse_{rd, pgm}_addr
|
2
|
cfg, tpgm, trd
|
3
|
tsu_h_{cs, ps, ps_cs}
|
3
|