Table: Egress Transaction Map summarizes AXI transaction mapping to PCIe domain.
To generate messages, the AXI-PCIe bridge provides registers. Refer to the AXI_PCIE_MAIN.TX_PCIE_MSG_* registers for details on generating these types of transactions in the Zynq UltraScale+ MPSoC Register Reference (UG1087) [Ref 4].
Note: Special handling is required by software for memory write transactions with ECRC errors. The PCI Express specification mandates that the ECRC errors be captured and signaled to the software. The error could be in the payload or in the header. If the payload is corrupted, a known location could receive incorrect data. If the address is corrupted, the transaction could end up at a completely incorrect slave. Software is required to read the header from the AER registers in the PCIe configuration space and take corrective action because, by the time software receives notification of such an event, the write transaction with the ECRC error could already be executed.