When the PS must be reset without resetting the PL, the PMU (only the PMU) must manage this reset sequence. Through the error mechanism in the PMU, all of the errors can be set to cause a PS only reset. The PMU asserts a signal to the PL power domain that blocks PS_PROG_B from assertion by the CSU. This bit is controlled by the PMU and can be set at the beginning of time or during an interrupt routine. Once this bit is set in the PMU, the only difference to the reset block in the LPD between a PS-only reset and a system-reset request is that the reset block in the LPD marks a different bit in the reset reason register when the PL is not reset.