Clock Tap Control Settings

Versal Adaptive SoC Technical Reference Manual (AM011)
Document ID
AM011
Release Date
2023-10-05
Revision
1.6 English

The three clock frequency ranges are shown in the following table.

Table 1. QSPI Clock Tap Delay Settings
Control QSPIx_CLK Frequency Range Register Bit Field
≤ 37.5 MHz >37.5 to 100 MHz >100 to 150 MHz
Data tap delay unit bypass

Bypass
(1)

Bypass
(1)

Enable
(0)

PMC_IOP_SLCR.IOP_TAPDLY_BYPASS [LQSPI_RX]
0: Enabled, use tap delay
1: Bypass
Clock loopback pin enable

Disable
(0)

Enable
(1)

Enable
(1)

LPBK_DLY_ADJ [USE_LPBK]1
0: Disable
1: Enable
Data tap delay settings 00, 000 00, 000 01, 000 LPBK_DLY_ADJ [DLY1], [DLY0]
Data delay enable Disable (0)

Enable
(1)

Disable
(0)

 DATA_DLY_ADJ [USE_DATA_DLY]
Data delay adjustment 000 000 000 DATA_DLY_ADJ [DATA_DLY_ADJ]
  1. If loopback is enabled, the QSPI_LPBK_CLK signal pin must be routed through the PMC MIO pin 6 and left unconnected on the PCB.
  2. The data delay enable bit is not used when the clock lookback pin is disabled, [USE_LPBK] = 0. However, the data delay enable bit is normally written = 0 when loopback is not used.